Abstract: A method of determining whether datapaths executing in a computer program should execute conditional processing block includes determining whether processor enable (PE) states of all of the datapaths are disabled, and branching around the conditional processing if the PE states of all of the datapaths are disabled. Branching is not performed, even if the PE states of all of the datapaths are disabled, if the program is determined to be deterministic. That determination is made by evaluating the state of a deterministic bit. Instructions are also provided for carrying out the determining and branching operations. The instructions may also be combined with operations that maintain the PE states during conditional processing.

Abstract: A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between the data items and a memory, a size of the array, and a number of remaining parallel passes of the datapaths in the loop processing operation. A computer instruction is also provided, which includes a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items. The instruction includes a count field that specifies the number of remaining parallel loop passes to process the array and a count field that specifies the number of serial loop passes to process the array. Different instructions can be used to handle different allocations of passes to parallel datapaths. The instruction also uses information about the total number of datapaths.

Abstract: A method of controlling the enabling of processor datapaths in a SIMD processor during a loop processing operation is described. The information used by the method includes an allocation between the data items and a memory, a size of the array, and a number of remaining parallel passes of the datapaths in the loop processing operation. A computer instruction is also provided, which includes a loop handling instruction that specifies the enabling of one of a plurality of processor datapaths during processing an array of data items. The instruction includes a count field that specifies the number of remaining parallel loop passes to process the array and a count field that specifies the number of serial loop passes to process the array. Different instructions can be used to handle different allocations of passes to parallel datapaths. The instruction also uses information about the total number of datapaths.

Abstract: An apparatus and method for processing portions of data words are described. Data words read from or written to memory are temporarily stored in a data register. Each data word is configured to include multiple portions which can be processed separately. For example, each full data word can be 32 bits long and can include four byte-long data portions. The data word is temporarily stored in a data register for processing. An address register associated with the data register temporarily stores an address word associated with the portion of the data word to be processed. The address word includes an address pointer for the portion of the data word as well as a tag. The tag includes information used to extract the portion of the data word from the data word for processing or to insert the portion of the data word into the data word after processing. The information in the tag can include the size of the data word portion being processed and its location within the data word.

Abstract: An apparatus and method for accessing data in a processing system are described. The system includes multiple processing elements for executing program instructions. The processing system can be a single instruction stream, multiple data stream (SIMD) system, and the processing elements can be the multiple data paths of the SIMD system. Each processing element or data path is associated with an identifying value which distinguishes it from the other elements. A memory, which can be configured as an interleaved memory including multiple memory banks, stores data accessed by the processing elements. The data can be a table used for table look-ups for such functions as mathematical operations. Also, multiple copies of the table can be stored in multiple respective banks of the memory. An instruction calling for a memory access such as a table look-up is received. The instruction contains address information which can be a starting address of a table in memory.