Abstract: Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a noncompliant connectivity grid, and forming via caps in association with the noncompliant connectivity grid in either a first direction or a second direction, which can be substantially orthogonal to the first direction in some embodiments. The via caps are configured to provide each via with an amount of overlap area for sufficient coverage. In some instances, the method also includes forming a configuration layer for routing among a subset of the vias to provide at least the amount of overlap area for each via in the subset, and for forming the via caps for unrouted vias that are not part of the subset.

Abstract: Various embodiments of the invention provide for cell structures having independently accessible circuit elements as a part of a customizable logic array device. In one embodiment, a cell forming a portion of a customizable logic array device includes a base layer, which, in turn, including circuit elements each having one or more inputs and one or more outputs. The cell also includes a configuration layer configured to form a logic device from one or more of the circuit elements. Further, the cell includes an interlayer connection layer configured to connect each of the inputs and the outputs to the configuration layer so as to enable each of the circuit elements to be independently accessible. Advantageously, the interlayer connection layer facilitates usage of each of the circuit elements to reduce the number of unused circuit elements in the cell.

Abstract: An in-circuit design and verification device, system and method are disclosed for cooperatively designing and verifying application-specific integrated circuit device prior to fabrication by emulating logical and specialized functions. By emulating specialized circuits of the ASIC, an in-circuit design and verification-device can advantageously detect errors that are not generally detectable by conventional techniques for verifying ASIC designs. In one embodiment, an in-circuit design and verification system includes programmable logic configured to emulate on-chip logic of an ASIC as well as a specialized function circuit configured to emulate a specialized function that the programmable logic cannot emulate. The in-circuit design and verification system also includes an emulation interface configured to exchange signals between the configured programmable logic and the specialized function circuit during in-circuit design and verification.