Abstract: Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission.

Abstract: A method, computer readable medium apparatus and system for developing an Application-Specific Integrated Circuit (“ASIC”) are disclosed. In one embodiment, a method includes defining the functionality of a target ASIC device within a target system, as well as synthesizing circuits for the target ASIC device and a programmable logic device concurrently or nearly concurrently, thereby providing a conversion-less ASIC development flow using one or more programmable devices. In a specific embodiment, the conversion-less ASIC development flow requires no subsequent step of modifying a functional description for the target ASIC device from a functional description expressed in terms of the programmable logic device, thereby reducing an amount of time required to produce the target ASIC device.