Patents Assigned to Chongqing GigaChip Technology Co., Ltd.
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Publication number: 20240120932Abstract: Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight.Type: ApplicationFiled: December 3, 2023Publication date: April 11, 2024Applicant: Chongqing GigaChip Technology Co., Ltd.Inventors: Yabo NI, Yong ZHANG, Xiaofeng SHEN, Ting LI, Lu LIU, Can ZHU, Jiahao PENG, Liang LI, Dongbing FU, Jianan WANG
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Publication number: 20240106447Abstract: Embodiments of the disclosure provide a circuit for online adaptive direct current offset correction, which includes: an analog adder circuit, a digital-to-analog conversion circuit, a direct current detection circuit, an adaptive update signal generating circuit, an output circuit, and a mode selection circuit. Embodiments of the present disclosure also provide a zero-IF receiver including a circuit for online adaptive DC offset correction.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Applicant: Chongqing GigaChip Technology Co., Ltd.Inventors: Youhua WANG, Fei LI, Kairang CHEN, Dongbing FU, Can ZHU
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Publication number: 20240021662Abstract: The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter.Type: ApplicationFiled: September 25, 2023Publication date: January 18, 2024Applicant: Chongqing GigaChip Technology Co., Ltd.Inventors: Rongbin HU, Can ZHU, Jianan WANG, Guangbing CHEN, Dongbing FU, Zhengping ZHANG, Zhou YU, Zhimei YANG, Min GONG
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Patent number: 11728820Abstract: The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.Type: GrantFiled: January 7, 2020Date of Patent: August 15, 2023Assignees: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Daiguo Xu, Hequan Jiang, Xueliang Xu, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Xiaoquan Yu, Shiliu Xu, Tao Liu
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Patent number: 11716091Abstract: A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.Type: GrantFiled: January 7, 2020Date of Patent: August 1, 2023Assignees: No. 24 Research Institute Of China Electronics Technology Group Corporation, Chongqing GigaChip Technology Co., Ltd.Inventors: Tao Liu, Jian'an Wang, Yuxin Wang, Shengdong Hu, Zhou Yu, Minming Deng, Daiguo Xu, Lu Liu, Dongbing Fu, Jun Luo, Xu Wang, Yan Wang, Zicheng Xu
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Publication number: 20230216502Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.Type: ApplicationFiled: January 6, 2021Publication date: July 6, 2023Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Ting LI, Gangyi HU, Ruzhang LI, Yong ZHANG, Yabo NI, Dongbing FU, Jian'an WANG, Guangbing CHEN
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Publication number: 20230198537Abstract: A follow-hold switch circuit comprising: a follower; a sampling sub-circuit for voltage sampling; a bootstrap-control sub-circuit, which provides a bootstrap voltage to the sampling sub-circuit when the circuit is in a following state; a sampling-switch-control sub-circuit, which provides a common-mode voltage to a bootstrap capacitor in the bootstrap-control sub-circuit when the circuit is in a holding state; the follower is connected to an output of the sampling sub-circuit; the sampling sub-circuit is connected to the bootstrap-control sub-circuit and the sampling-switch-control sub-circuit respectively through a sampling switch; the present disclosure can effectively improve the linearity of sampling switches.Type: ApplicationFiled: January 19, 2021Publication date: June 22, 2023Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Daiguo XU, Dongbing FU, Zhengping ZHANG, Zhou YU, Jian'an WANG, Can ZHU, Ruzhang LI, Guangbing CHEN, Yuxin WANG, Xueliang XU
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Publication number: 20230198475Abstract: A differential-follower control circuit has been provided, comprising: a follower; an output-voltage following module, which controls a voltage at a control terminal of the follower to vary with an output voltage; a substrate-voltage following module, which controls a substrate voltage of an output transistor of the follower to vary with an input voltage; an output terminal of the follower is connected to a first terminal of the output-voltage following module; a second terminal of the output-voltage following module is connected to the control terminal of the follower; a first terminal of the substrate-voltage following module is connected to an input terminal of the follower and a second terminal of the substrate-voltage following module is connected to a substrate of the output transistor; the invention effectively improves the overall linearity of the follower.Type: ApplicationFiled: January 19, 2021Publication date: June 22, 2023Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Daiguo XU, Dongbing FU, Zhengping ZHANG, Zhou YU, Jian'an WANG, Can ZHU, Ruzhang LI, Guangbing CHEN, Yuxin WANG, Xueliang XU
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Patent number: 11664794Abstract: The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.Type: GrantFiled: January 7, 2020Date of Patent: May 30, 2023Assignees: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Ting Li, Zhengbo Huang, Yong Zhang, Yabo Ni, Jian'an Wang, Guangbing Chen, Dongbing Fu, Zicheng Xu
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Patent number: 11558064Abstract: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.Type: GrantFiled: January 7, 2020Date of Patent: January 17, 2023Assignees: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: Daiguo Xu, Hequan Jiang, Ruzhang Li, Jianan Wang, Guangbing Chen, Yuxin Wang, Dongbing Fu, Liang Li, Yan Wang
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Patent number: 11476803Abstract: The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents, and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the senType: GrantFiled: January 7, 2020Date of Patent: October 18, 2022Assignees: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: Rongbin Hu, Ziqiang Yi, Gang Zhou, Dong Tang, Ning Tang, Daiguo Xu, Jianan Wang, Guangbing Chen, Dongbing Fu
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Publication number: 20220247423Abstract: SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.Type: ApplicationFiled: January 7, 2020Publication date: August 4, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: DAIGUO XU, HEQUAN JIANG, RUZHANG LI, JIANAN WANG, GUANGBING CHEN, YUXIN WANG, DONGBING FU, LIANG LI, YAN WANG
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Publication number: 20220247354Abstract: The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents.Type: ApplicationFiled: January 7, 2020Publication date: August 4, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: RONGBIN HU, ZIQIANG YI, GANG ZHOU, DONG TANG, NING TANG, DAIGUO XU, JIANAN WANG, GUANGBING CHEN, DONGBING FU
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Publication number: 20220224320Abstract: The present disclosure provides a substrate-enhanced comparator and electronic device, the comparator including: a cross-coupled latch, for connecting input signals to the gate of a cross-coupled MOS transistor to form a first input of the latch; output buffers, connected to the cross-coupled latch for amplifying output signals of the latch; AC couplers, connected to the output buffers for receiving and amplifying the output signals of the latch, coupling the output signals to substrates of the cross-coupled MOS transistors to form second inputs of the latch. The cross-coupled latch is also for output signal regenerative latching based on input signals sampled at the first inputs and input signals sampled at the second inputs. The present disclosure introduces additional substrate inputs to the cross-coupled structure of the conventional latch as the second inputs of the latch.Type: ApplicationFiled: January 7, 2020Publication date: July 14, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Ting LI, Zhengbo HUANG, Yong ZHANG, Yabo NI, Jian'an WANG, Guangbing CHEN, Dongbing FU, Zicheng XU
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Publication number: 20220224350Abstract: A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.Type: ApplicationFiled: January 7, 2020Publication date: July 14, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Tao LIU, Jian'an WANG, Yuxin WANG, Shengdong HU, Zhou YU, Minming DENG, Daiguo XU, Lu LIU, Dongbing FU, Jun LUO, Xu WANG, Yan WANG, Zicheng XU
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Patent number: 11353505Abstract: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK?) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK?) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.Type: GrantFiled: January 7, 2020Date of Patent: June 7, 2022Assignees: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: Mingyuan Xu, Liang Li, Jun Liu, Xiaofeng Shen, Jianan Wang, Dongbing Fu, Guangbing Chen, Xingfa Huang, Xi Chen
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Patent number: 11349489Abstract: An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the ith pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline.Type: GrantFiled: January 7, 2020Date of Patent: May 31, 2022Assignees: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: Yong Zhang, Ting Li, Zhengbo Huang, Yabo Ni, Dongbing Fu
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Publication number: 20220094366Abstract: An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the ith pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline.Type: ApplicationFiled: January 7, 2020Publication date: March 24, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: YONG ZHANG, TING LI, ZHENGBO HUANG, YABO NI, DONGBING FU
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Publication number: 20220091184Abstract: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK?) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK?) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.Type: ApplicationFiled: January 7, 2020Publication date: March 24, 2022Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, CHONGQING GIGACHIP TECHNOLOGY CO. LTD.Inventors: MINGYUAN XU, LIANG LI, JUN LIU, XIAOFENG SHEN, JIANAN WANG, DONGBING FU, GUANGBING CHEN, XINGFA HUANG, XI CHEN
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Publication number: 20210391870Abstract: The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.Type: ApplicationFiled: January 7, 2020Publication date: December 16, 2021Applicants: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.Inventors: Daiguo XU, Hequan JIANG, Xueliang XU, Jian'an WANG, Guangbing CHEN, Dongbing FU, Yuxin WANG, Xiaoquan YU, Shiliu XU, Tao LIU