Abstract: Apparatus and associated methods relate to configuring a circuit to sense current in a low-cost non-precision resistance, calibrating the circuit to correct inaccuracy measured in the sensed current, and measuring with the corrected circuit the precise current sensed in the low-cost non-precision resistance. In an illustrative example, the low-cost non-precision resistance may be a metal trace on a printed circuit board. The circuit may be calibrated, for example, over a range of currents or temperatures, permitting automatic adjustment to a wide range of non-precision resistance parameter values and environmental conditions. In some examples, correcting coefficients may be adapted to compensate for resistance non-linearities, which may include skin effect or self-heating. Some embodiments may verify the calibrated correction over a range of current and temperature.

Abstract: A method, system, and apparatus of a balanced rotator conversion of serialized data are disclosed. In one embodiment, a method to convert serialized data includes acquiring a rotator module output, and generating a balancing signal with a reference module, which operates with a reference frequency. The method further includes processing the rotator module output and the balancing signal in an interpolation module to generate a balanced rotator output. The method may include a rotator module output that is generated by an analog phase rotator when a control voltage is received by the analog phase rotator. The reference module may include an other analog phase rotator to generate a balancing signal. The interpolation module may interpolate the balancing signal and the rotator module output to modulate a phase of the balanced rotator output. The balanced rotator output may include an orthogonal output.

Abstract: A fully-integrated tuner for performing signal channel selection and image rejection in an analog cable television system is provided. Various embodiments disclose a tuner including an analog RF section to process an analog RF input signal and generate complex low intermediate frequency digital signals, and a signal processing section configured to reduce image and signal leakage in the complex low intermediate frequency signals. The signal processing section selects a signal channel of the complex low intermediate frequency signals and suppresses channel components adjacent to the signal channel. In one embodiment, the signal processing section includes a complex digital signal channel select filter to select the signal channel and suppress the adjacent channel components. In other embodiments, the complex digital signal channel select filter selects the signal channel, shapes the selected signal channel to generate a shaped signal channel, and equalizes a group delay of the shaped signal channel.

Abstract: Systems and methods regarding the restoration of serialized data to parallel data with a low speed reference signal are provided. In exemplary embodiments, a phased lock loop receives a reference clock signal from a data source and generates a reference high speed clock signal based on the reference clock signal. A dynamic link library clock and data recovery module reads and writes data flows contained within serialized data onto parallel data paths at a modified high speed clock signal based on the reference high speed clock signal.

Abstract: A dual-mode analog baseband circuit is implementable on a single IC with reduced chip area. The baseband portion of the IC includes a single dual-mode complex filter that is reconfigurable to be a filter for Bluetooth signals or for wireless local area network (wireless LAN) format signals, such as 802.11b, and includes a single dual-mode amplifier that is reconfigurable to amplify Bluetooth signals or wireless LAN format signals.

Abstract: A dithering system yielding two-dimensional dither functioning is implemented without line memories. For each primary input color, a feedback loop outputs an color input signal plus error that can be preset to different values. The desired result is that vertical artifacts on a display formed from the output signals are relocated to different locations on consecutive display lines. If signal magnitude from the feedback loop output exceeds the magnitude of the video system creating the display, signal magnitude is preset to a value representing error at the start of the display line.

Abstract: An adaptive intra-field algorithm to de-interlace video data uses two line memories to implement a median filter that can use multiple data points on adjacent lines of display. In a median-mode, the filter outputs the median of the input data to create the value for a location on the intermediate line and can decrease image blurring. But if examination of the two adjacent pixels on two adjacent scan lines is small, as in the case of a vertical image line, the filter operates as a line average filter, to avoid creating image artifacts.

Abstract: A sub-system and method to receive input image pixel amplitude data at an input pixel resolution and to output image pixel amplitude data in one or two dimensions at a higher pixel resolution includes a computer system-executable algorithm with user-programmable coefficients. The programmable coefficients are user-selectable according to the nature and quality of the input image data such that sharpness of the output image data can be at least partially tailored to the image.

Abstract: A bad pixel detection and correction system and method in which two estimates are computed in real time for the value of a given pixel. The two estimates are based on the values of pixels surrounding the given pixel. One of the estimates is a minimum value and the other of the two estimates is a maximum value. When the value of the given pixel exceeds the maximum value, the given pixel value is reset to the maximum value. When the value of the given pixel is less than the minimum value, the given pixel value is reset to the minimum value. Otherwise, the given pixel value is not changed. The given pixel value after updating is injected in real time into the stream of pixel data provided for additional graphics processing, such as RGB interpolation. This prevents bad pixel data from affecting the values of other pixels computed in the additional graphics processing. The bad pixel detection and correction system can operate with both monochrome and color pixel data.

Abstract: A nominal 50% duty cycle input CLKIN clock signal is processed by an adaptive circuit that outputs complementary CLK and CLKB clock signals whose duty cycle is continuously and automatically maintained at substantially 50%. The circuit includes a duty cycle adjustor circuit comprising inverter stages whose VTH is adjusted by a control voltage VC to vary duty cycle of the CLKIN signal passing through the stages. The inverter output signal is converted to the differential CLK, CLKB signals, which are low pass filtered to obtain DC voltages that are input to a differential operational amplifier whose output is control signal VC. Using the ensured substantially 50% duty cycle for CLK (or CLKB) enables data to be clocked or latch-transferred between IC stages substantially error free even if IC stage setup time varies, and clock frequency is increased. CLK duty cycle can be held to 50%±0.1% even if CLKIN duty cycle varies from 33% to 67%.

Abstract: A sub-system and method to receive input image pixel amplitude data at an input pixel resolution and to output image pixel amplitude data in one or two dimensions at a higher pixel resolution includes a computer system-executable algorithm with user-programmable coefficients. The programmable coefficients are user-selectable according to the nature and quality of the input image data such that sharpness of the output image data can be at least partially tailored to the image.

Abstract: A two-dimensional (2D) filter is disclosed that accomplishes flicker filtering with virtually no loss of image resolution. The 2D filter operates without adaption and only on the non-detail portions of the original image. The filter works first in the horizontal (x-axis) direction by separating the high-pass (detail, high-resolution) image elements from the low-pass (blurred, low-resolution) elements. A vertical (y-axis) flicker filter is applied to the low-pass elements and the result is summed with the high-pass elements. Thus, the detail elements are not subjected to flicker filtering and, as a result, remain well-defined while flicker is eliminated from the overall image.

Abstract: A high speed analog color key detection system is disclosed for video/graphics mixing that employs a high speed analog strobe comparator to compare the analog version of a pre-defined color key value to the stream of pixel values in an incoming analog graphics signal. When the comparator indicates a match, the display signal is switched from the analog graphics signal to an incoming analog video signal, enabling the analog video signal to be displayed within a graphics window. Comparisons are triggered by active transitions of a strobe signal with a frequency that is an integer k multiple of the frequency at which the pixel values are generated by a graphics card. Oversampling strobe signals (where the integer k is greater than one) enable comparisons to be performed on small segments of fat pixel values. The strobe signal is generated using a phase locked loop that is synchronized with a horizontal synchronization signal provided by the graphics card.

Abstract: A clock-referenced switching bias current source is disclosed wherein an accurate bias current is established based on the charge dissipated by a switching capacitor over a predetermined period. The time period is established by a very accurate system clock. The value of the capacitor can be accurately selected with .+-.10%. By selecting a particular capacitance and frequency, a desired average bias current value is determined according to the amount of charge dissipated over the predetermined period. In different embodiments, the bias current source can be configured to provide a bandgap current that is temperature and/or process independent.

Abstract: A method and system is disclosed for scaling computer video in the process of scan rate conversion. In the disclosed system and method storage is provided for at least two lines of graphics pixels per video component composing the computer graphics signals and less than a full frame's worth of the graphics pixels. The graphics pixels are stored as they are provided so that the newest graphics pixels or a linear combination of the newest graphics pixels and stored graphics pixels overwrite previously-stored graphics pixels. In a repeating pattern for every RV VGA lines, where RV.gtoreq.2, television pixels composing the television video signals are generated from a weighted sum of the stored graphics pixels such that a different precomputed set of weights are used to compute the television pixels for each of the generated television lines.

Abstract: An active pixel sensor implemented with CMOS technology that employs a plurality of photocells, each including a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode. Each photocell includes a switching network that couples the photocurrent to the storage node only during the integration period while ensuring that a relatively constant voltage is maintained across the photodiode during integration and non-integration periods. The transistors in the switching network operate in a forward active subthreshold region, ensuring linear operation and the diode voltage is clamped to a small positive voltage so that the diode is always reverse-biased. A source-follower generates a output signal correlated to the charge on the storage node that is coupled to column output circuitry that samples the signal.

Abstract: A method and system is disclosed for scaling computer video in the process of scan rate conversion. In the disclosed system and method storage is provided for at least two lines of graphics pixels per video component composing the computer graphics signals and less than a full frame's worth of the graphics pixels. The graphics pixels are stored as they are provided so that the newest graphics pixels or a linear combination of the newest graphics pixels and stored graphics pixels overwrite previously-stored graphics pixels. In a repeating pattern for every M television lines, where M>2, television pixels composing the television video signals are generated from a weighted sum of the stored graphics pixels such that a different precomputed set of weights are used to compute the television pixels for each of the M television lines. The television signals are horizontally and vertically scaled so the graphics image corresponding to the computer graphics signals being converted fits within a television display.

Abstract: A graphics subsystem converts a first graphics data stream for display on a computer monitor having a first refresh rate into a second graphics data stream for a television monitor having a second, slower refresh rate. The graphics subsystem has a first memory for storing one horizontal scan line of pixel data and a second memory for storing one half of a horizontal scan line of pixel data. Multiplexers direct data to a first summing circuit from an input port and from the first memory itself, so that a first horizontal line of input pixel data is initially stored in the first memory and a second horizontal line of input pixel data is combined with the first horizontal line of data by the first summing circuit, and the resulting combined pixel data is stored in back into the first memory. A controller sends the combined pixel data from the first memory to a second summing circuit while a next horizontal line of input pixel data is received.

Abstract: A color space converter is implemented using current mode analog circuitry to efficiently transform video data from a YC.sub.b C.sub.r format to an RGB format in order to allow the display of video signals on a color monitor. The analog current-mode circuitry is implemented in an integrated circuit that will operate at high clock rates and can be integrated in a small die area so as to reduce its cost. The color space converter includes Y, C.sub.b and C.sub.r current-mode conversion circuits to compute Y, C.sub.b and C.sub.r contributions to the G, R and B signals, and current-mode adders that add those contributions to the G, R and B signals to generate the G, R and B signals. Each conversion circuit includes (A) a respective folded cascode structure having an input coupled to a respective analog Y, C.sub.b or C.sub.r signal, each conversion circuit generating a respective Y, C.sub.b or C.sub.r current output; (B) at least one respective current mirror that generates from the Y, C.sub.b or C.sub.

Abstract: A RAMDAC circuit drives a display device so as display multiple modes of color depth and display resolution in a single display frame without sacrificing resolution of the higher-resolution mode, and adjusts the output pixel rate to match that of the display mode being display on a pixel-by-pixel basis. The RAMDAC circuit switches between two graphics modes on-the-fly on a pixel-by-pixel basis in accordance with mode control bits stored in the pixel data. Furthermore, the RAMDAC circuit switches between two output pixel rates such that the amount of video memory used for any predefined screen area remains constant even though the output pixel rate and resolution are dynamically adjusted.