Abstract: A hierarchical structure for a non-hierarchical, non-ordered second representation of a circuit design is generated from a first hierarchical representation and a set of generation rules. Subsequently, the newly generated hierarchical structure is populated by design components to provide a second hierarchical representation. This second hierarchical representation enables comparison between the reference hierarchical structure and the new hierarchy representation to determine equivalence of the circuit designs associated with the new generated and reference hierarchical structure.
Type:
Grant
Filed:
May 10, 1999
Date of Patent:
March 4, 2003
Assignee:
Chrysalis Symbolic Design, Inc.
Inventors:
John W. Hagerman, Matthew J. Bellantoni, Richard J. Cloutier
Abstract: A design verification system verifies whether first and second representations of a circuit design match. The system includes a processor assembly and a memory that stores a first hierarchy of elements as the first representation of the design, a second hierarchy of elements as the second representation of the design, and a map entry that identifies a correspondence between an element of the first hierarchy and an element of the second hierarchy.
Type:
Grant
Filed:
April 3, 1998
Date of Patent:
April 17, 2001
Assignee:
Chrysalis Symbolic Design, Inc.
Inventors:
John Hagerman, Matthew Bellantoni, Richard J. Newton, II, Richard J. Cloutier, Gerard Memmi