Abstract: Switching node regulator for sfp ethernet adaptor. A method is disclosed for regulating voltage on an integrated circuit formed on a substrate to power circuitry on the substrate. An unregulated power supply is provided as an input to the integrated circuit connected between a positive node and a reference node on the integrated circuit. Current is sourced in a first current sourcing step through drive circuitry on the substrate from the positive node to an inductor/capacitor reactive circuit external to the integrated circuit. The output of the inductor/capacitor reactive circuit comprises a filtered regulated power supply voltage that is operable to power at least a portion of the circuitry on the substrate. Current is sourced in a second current sourcing step through the drive circuitry on the substrate from the reference node to the inductor/capacitor reactive circuit when the current in the inductor is ramping down.

Abstract: Reduced GMII with internal timing compensation A data interface between first and second integrated circuits. An internal clock signal is generated internal to the first integrated circuit and operates in a first frequency. A data generator is provided for generating data from at least one edge of the internal clock for transmission to the second integrated circuit. a first delay block internal to the first integrated circuit delays the internal clock for a predetermined duration of time less than one-half clock cycle of said internal clock to provide a first delayed clock. The second integrated circuit is then operable to receive the transmitted first delayed clock and utilize the transmitted first delayed clock to sample the received data generated by the data generator.