Abstract: A Point of Local Repair (PLR) network element includes one or more ports and circuitry connected thereto for forwarding and control, wherein the circuitry is configured to receive a PATH message for a Label Switched Path (LSP) tunnel in a Multiprotocol Label Switching (MPLS) network with a specified DiffSery Traffic Engineering (DSTE) Class Type, determine the DSTE Class Type based on the PATH message, and store the DSTE Class Type for the LSP tunnel to ensure a Facility Bypass tunnel used for the LSP tunnel supports the specified DSTE Class Type. The circuitry can be further configured to, responsive to a failure of the LSP tunnel, select the Facility Bypass tunnel for the LSP tunnel such that the Facility Bypass tunnel supports the specified DSTE Class Type.

Abstract: A silicon modulator where the doping profile varies along the lateral and/or longitudinal position in the transition zones to achieve improved performance in terms of either optical attenuation or contact access resistance or both. A silicon-based modulator includes a waveguide including a contact region and a core region, wherein the waveguide includes a dopant concentration that decreases from the contact region to the core region in a transition zone according to a doping profile that is variable.

Abstract: A loss-based wavelength meter includes a first photodiode configured to measure power of monochromatic light; and a loss section having a monotonic wavelength dependency, wherein a wavelength of the monochromatic light is determined based on measurements of the first photodiode after the monochromatic light has gone through the loss section. This provides a compact implementation that may be used in integrated optics devices using silicon photonics as well as other embodiments.

Abstract: Systems and methods include receiving network topology information of a network including a plurality of routers; receiving link measurements defining bandwidth on links in the network; determining routes in the network based on the network topology information; and utilizing the routes and the link measurements to determine an estimate of an initial traffic matrix that includes the bandwidth between origin routers and destination routers.

Abstract: Systems and methods for analyzing root-causes of Wi-Fi issues in a Wi-Fi system associated with a Local Area Network (LAN) are described in the present disclosure. A method, according to one embodiment, includes a step of monitoring a Wi-Fi system associated with a LAN to detect authentication failures in the Wi-Fi system. In response to detecting an authentication failure in the Wi-Fi system, the method also includes the step of analyzing the authentication failure to determine one or more root-causes of the authentication failure. The method also includes pushing changes to the Wi-Fi system to automatically remediate the one or more root-causes in the Wi-Fi system.

Abstract: First and second waveguide structures are coupled to a waveguide coupling structure, the first waveguide structure comprising a first guiding core structure formed on a first cladding structure, and a second cladding structure formed on the first guiding core structure. The first and second waveguide structures have respective guiding ridges. The second waveguide structure comprises a second guiding core structure formed on a third cladding structure, and a fourth cladding structure formed on the second guiding core structure. The waveguide coupling structure comprises a transition structure, a multimode interference structure between the transition structure and the second waveguide structure, and an electrode over at least a portion of the guiding ridge within the second cladding structure and over at least a portion of the transition structure.

Abstract: Transaction validation includes assigning respective asset stake values to computing assets of network services. A request to assign a transaction validation stake to a transaction validator is received. At least some of the computing assets are assigned to the transaction validator. Responsive to a request for one or more transaction validators, a response that includes an indication of the transaction validator is provided. The transaction validator is selected using the respective asset stake values of the at least some of the computing assets that are assigned to the transaction validator.

Abstract: Systems and methods for strategizing the insertion and/or removal of a node into and/or out of a network are provided. A system, according to one implementation, includes a processing device and a memory device configured to store a computer program. The computer program includes instructions that, when executed, enable the processing device to configure a Network Element (NE) in a pass-through mode whereby channels are neither added nor dropped to thereby prepare the NE for insertion into or removal from a photonic network. Upon the insertion of the NE into the photonic network or the removal of the NE from the photonic network, the instructions may further enable the processing device to perform a zero configuration procedure for automatically establishing communication along one or more Optical Service Channels (OSCs) and for automatically controlling gain and loss characteristics along one or more fiber links altered by the insertion or removal.

Abstract: A network timing view provides enhanced visualization for synch timing in support of mobile (4G/5G deployments) and others requiring sync. It allows network managers to view relevant synch data both textually and graphically displayed on the network map nodes and links in a unified view. The user is able to select the appropriate filter on the network map to show the 1588/SyncE connectivity and relevant nodes that are participating in delivering timing. It allows a user to trace the timing path from any timing device upstream to the clock source. It also allows the user to interactively discover and navigate downstream timing paths from any timing device, similar to exploring a tree hierarchy. The timing topology and path data provided allows a user to investigate the timing network for troubleshooting purposes such as timing alarms and events, sync problems, clock quality levels and clock states.

Abstract: Systems and methods include receiving a plurality of symbols that are part of a defined Digital Signal Processing (DSP) frame for coherent optical communication, wherein the DSP frame structure has a messaging channel incorporated therein that includes a subset of the plurality of symbols; capturing multiple samples of the messaging channel; and determining a message in the messaging channel based on analysis of the multiple samples. The method can further include transmitting, in the messaging channel, a reply to the message with the reply being repeated multiple times. The analysis is performed prior to Forward Error Correction (FEC) decoding on the data path.

Abstract: Systems and methods for extending Ethernet Virtual Private Network (EVPN) protocols are provided. A Link Aggregation Group (LAG), according to one implementation, includes a plurality of Ethernet Segments (ESs) and a plurality of service ports configured to communicate over the plurality of ESs. The service ports are configured to enable an operator device to access an EVPN to receive Layer 2 (L2) and Layer 3 (L3) Ethernet services. Also, the service ports are configured to enable the operator device to operate with multi-homing functionality to receive the L2 and L3 Ethernet services via redundant paths associated with the plurality of ESs. The services ports are further configured to respond to operator commands, whereby the operator commands include one or more operator commands related to switching among the redundant paths.

Abstract: Optical line amplifiers with on-board controllers and supervisory devices for controlling optical line amplifiers are provided for controlling bootstrap or power-up procedures when optical line amplifiers are initially installed in an optical communication network. The controllers may include non-transitory computer-readable medium configured to store computer logic having instructions that, when executed, cause one or more processing devices to block an input to one or more gain units of the line amplifier and cause the line amplifier to operate in an Amplified Spontaneous Emission (ASE) mode. In response to a detection of a valid power level of the line amplifier, the instructions can further cause the one or more processing devices to switch the line amplifier from the ASE mode to a regular mode and unblock the input to the one or more gain units of the line amplifier to allow operation of the line amplifier in the regular operating mode.

Abstract: Systems and methods for enabling Media Access Control Security (MACsec) at a MAC layer, according to IEEE 802.1AE, and extending MACsec are provided. An edge device, according to one implementation, includes one or more User-to-Network Interface (UNI) ports and a plurality of Network-to-Network Interface (NNI) ports. The edge device also includes a processing device and a memory device configured to store a computer program having instructions. The instructions, when executed, allow the processing device to provide network security on a Media Access Control (MAC) layer, the network security defined by the MAC Security (MACsec) protocol. The instructions also allow the processing device to provide network path protection by enabling packet routing over multiple paths via the plurality of NNI ports on a network layer.

Abstract: An article of manufacture, having a semiconductor layer and a dielectric layer. The semiconductor layer comprising a first surface and a second surface. The dielectric layer located adjacent to the first surface of the semiconductor layer. One or more base portions of the semiconductor in direct contact with and extending from the dielectric layer. One or more collector portions of the semiconductor in direct contact with and extending from the dielectric layer. One or more emitter portions of the semiconductor in direct contact with and extending from the dielectric layer. The one or more collector portions are spaced apart from the one or more emitter portions by the one or more base portions.

Abstract: Driving an optical modulator is described. A control circuit generates first and second input voltages based on a target phase modulation between first and second optical waveguide arms of the optical modulator. An offset control circuit generates first and second offset signals. A linear modulator driver receives the first and second offset signals, generates a first output voltage for biasing the first optical waveguide arm using the first offset signal, and generates a second output voltage for biasing the second optical waveguide arm using the second offset signal. Feedback circuitry can feed the first and second output voltages to the offset control circuit, which can generate the first and second offset signals using the first and second output voltages. The output voltages bias the waveguide arms so the optical modulator operates close to the target phase modulation, even in the presence of manufacturing errors.

Abstract: In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

Abstract: Systems and methods for avoiding fiber damage of an optical fiber link are provided. A method, according to one implementation, includes monitoring optical signals transmitted along an optical fiber link from an output port of a first card to an input port of a second card. In response to detecting a fiber disconnection state when an amplifier of the first card is operating in a normal condition, the amplifier of the first card enters a forced Automatic Power Reduction (APR) condition. In addition to potentially reducing the risk of eye damage from laser light emitted from the optical fiber link, the forced APR condition is configured to allow for an uninterrupted debugging procedure. Also, the method includes returning the amplifier of the first card from the forced APR condition back to the normal operating condition after receiving an indication that the fiber disconnection state has cleared.

Abstract: An optical module for use in an optical system is disclosed, the optical module implementing Precision Time Protocol (PTP) clock functionality therein. The optical module includes an electrical interface with the optical system; circuitry connected to the electrical interface and configured to implement a plurality of functions of functionality; an optical interface connected to the circuitry; and timing circuitry connected to the electrical interface and one or more of the plurality of functions, wherein the timing circuitry is configured to implement the PTP clock functionality.

Abstract: A micro-optical connector holder with an integrated mating system for an optical assembly, typically on a modem PCBA. The integrated mating system is used to hold the micro-optical connectors together during assembly and to apply constant pressure keeping the connectors fully mated. The invention also uses a spring-pin mechanism to keep the holder lid and connectors in place without the use of screws or glue to make assembly easier. The integrated mating system allows the micro-optical connectors to be easily installed and uninstalled for manufacturing and testing purposes. The connector plugs and connector receptacles are aligned and secured by the integrated connector holder.

Abstract: A network element (16) includes ingress optics (22) configured to receive a client signal; egress optics (30) configured to transmit packets over one or more Ethernet links (20) in a network (12); circuitry (26, 28) interconnecting the ingress optics (22) and the egress optics (30), wherein the circuitry is configured to segment an Optical Transport Network (OTN) signal from the client signal into one or more flows; and provide the one or more flows to the egress optics for transmission over the one or more of Ethernet links (20) to a second network element (18) that is configured to provide the one or more flows into the OTN signal.