Abstract: Systems and methods of laying out integrated circuits are disclosed. During the layout stage of an integrated circuit device, a fixed, physical geometry is created of the parameterized cells (PCells) included in the integrated circuit schematic. The systems include a proxy engine configured to save to cache the geometries created during the layout stage such that the geometries need not be recomputed when the design is opened after a save to disk operation, during which geometries may otherwise be destroyed. The proxy engine may further be configured to delegate requests for the creation of geometries to other components of the integrated circuit design system. In addition, the proxy engine may be configured to perform customized evaluations of PCells, other than or in addition to caching and delegation.

Abstract: Exemplary systems and methods of laying out integrated circuits are disclosed. The systems include a layout application configured to place geometries in conformance with layout constraints transformed into composite cells. A composite cell defines a relationship between one or more cells, such as parameterized cells, and is independent of the physical topology of the cells. The exemplary systems are configured to use the composite cells to restrict a number of possible layout scenarios by generating a first layout scenario in conformance with the composite cell implementations, and to thereafter generate a second layout scenario in conformance with the constraints on all cells within the first layout scenario.