Abstract: Due to code constraints and pickup limitations of optical pickups, much of the signal energy of a binary coded analog signal, and therefore much of the information content, has dissipated at frequencies above about one-half (or even above about one-fourth) of the sampling frequency fs. For example, the response of data streams from DVD layers falls off by about 40 dB by fs/4 while the response of a CD data stream falls off by about 18 dB by fs/4. Thus, a data channel is provided in which the sampling rate fs is less than the channel bit rate fb. The data channel may be part of an optical storage drive in which data has been RLL encoded at d?0 and the sampling rate may be one-half the channel bit rate. Preferably, a sequence detector is employed which outputs two channel bits for each input sample.

Abstract: A simplified digital implementation of a fourth order Linkwitz-Riley crossover network is provided using approximations and transformations of the classical form. The approximation is particularly beneficial when the crossover frequency is low relative to the digital sampling rate, such as when an audio stream is split between bass and treble at about 30-300 Hz and the sampling frequency is about 100 times the cutoff frequency or higher. Rather than merely cascading two sets of second order filters, such as Butterworth filters, a fourth order transfer function is more directly implemented. Conventional transfer functions are simplified through approximations resulting in the elimination of all except one parameter, c, which is a linear function of the cutoff frequency. Additionally, multipliers are moved in line with the integrator elements.

Abstract: An integrated circuit on a system board is used, for example, in a digital audio device (such as a DVD or A/V receiver). The integrated circuit includes a digital-to-analog converter and the system board may include circuitry to mute the analog output of the device under certain predefined conditions. Because it may not be known in advance by the designer of the integrated circuit whether the circuit is activated by a signal in a high state (polarity) or a low state, the integrated circuit includes a detector which detects and stores the required polarity. When it is necessary for the circuit to be activated, the detector provides a signal of the correct polarity.

Abstract: Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.

Abstract: An integrated circuit, in which one or more internal parameters may be automatically configured for a particular application, includes a plurality of program select pins, each being in a predetermined fixed state, and at least one configuration pin associated with a parameter to be adjusted. Jumpers on the system board to which the integrated circuit is mounted connect the mounting pad of each configuration pin with the mounting pad of a selected program select pin. Consequently, when the integrated circuit is mounted on the system board, each configuration pin receives a selected value which internal configuration circuitry detects and causes the corresponding parameter to be adjusted accordingly. Any of the program select pins may have functions in addition to the configuration function. When the system board is powered on or undergoes a reset, a processor internal to the chip scans each the configuration pin to determine its value.

Abstract: An integrated circuit on a system board is used, for example, in a digital audio device (such as a DVD or A/V receiver). The integrated circuit includes a digital-to-analog converter and the system board may include circuitry to mute the analog output of the device under certain predefined conditions. Because it may not be known in advance by the designer of the integrated circuit whether the circuit is activated by a signal in a high state (polarity) or a low state, the integrated circuit includes a detector which detects and stores the required polarity. When it is necessary for the circuit to be activated, the detector provides a signal of the correct polarity.

Abstract: An apparatus and method for converting digital input signals sampled at different rates to analog signals includes a digital to analog converter for each digital input signal. Each digital to analog converter receives a digital input signal and a clock signal corresponding to the sampling rate of the received digital input signal. The apparatus can also receive a set of sample rate signals indicating the sampling rate for each digital input signal. The sample rate signals are used to route each digital input signal, along with a corresponding clock signal, to a corresponding digital to analog converter (DAC). A clock error signal controls routing of the digital input signals to the DACs as well as operation of the DACs. A clock divider and ratio detector module generates the clock error signal based on intermediate clock error signals that correspond to the sample rates.

Abstract: A high swing cascode bias circuit is provided for use within an integrated circuit. The bias circuit utilizes a start up transistor. The use of the start up transistor allows for high swing at the bias circuit outputs even though only one current source is provided from a reference bias circuit. The bias circuit may be powered down in response to a power down control signal. When the bias circuit is activated a plurality of bias signals may be provided to operating circuits of the integrated circuit.

Abstract: In a disk storage system for digital computers (e.g., optical or magnetic disk drives) a sampled amplitude read channel is disclosed comprising a convolutional code channel encoder for encoding check bits into channel data recorded to a disk storage medium, a trellis sequence detector for detecting a preliminary sequence from read signal sample values generated during read back, a convolutional code syndrome generator for generating an error syndrome from the preliminary sequence, and a post processor for evaluating the error syndrome to detect and correct errors made by the trellis sequence detector. The post processor remodulates the preliminary sequence output by the trellis sequence detector into a sequence of estimated sample values which are subtracted from the actual read signal sample values to form a sequence of sample errors.

Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated data sequence from a sequence of read signal sample values generated by an analog read signal emanating from a read head positioned over the disk storage medium. A sampling device samples the analog read signal to generate the read signal sample values, and a discrete-time equalizer equalizes the read signal sample values according to an asymmetric partial response target comprising a dipulse response of the form: (. . . , 0, 0,+X0,+X1,−X2,−X3,−X4, 0, 0, . . . ) where X0−X4 are non-zero to thereby generate equalized sample values. In the embodiments disclosed herein, X0−X4 are 2,2,1,2,1 respectively. A discrete-time sequence detector detects the estimated data sequence from the equalized sample values.

Abstract: A sampled amplitude read channel is disclosed for writing data to and reading data from a disk storage medium. A first channel encoder encodes a first j-k bits of a j-bit data block to generate first encoded data, and an ECC encoder encodes the first encoded data and a remaining k-bits of the data block to generate ECC redundancy symbols comprising a plurality of bits. A second channel encoder encodes the remaining k-bits of the data block and the ECC redundancy symbols to generate second encoded data. The first encoded data and the second encoded data are then output as channel data written to the disk storage medium.