Abstract: There is described a two-terminal multi-level memristor element synthesised from binary memristors, which is configured to implement a variable resistance based on unary or binary code words. There is further described a circuit such as a synapse circuit implemented using a multi-level memristor element.

Abstract: A system and method may include a battery, at least one component electrically coupled to and powered from the battery, a coil located proximate to the battery such that a temperature of the coil is indicative of a temperature of the battery, a coil resistance and battery temperature reporting system electrically coupled to the coil and configured to monitor a direct current resistance of the coil and estimate a temperature of the coil based on the direct current resistance, and a power management system communicatively coupled to the coil resistance and battery temperature reporting system, the battery, and the at least one component and configured to control power delivered and consumed by the battery and the at least one component based on the temperature of the coil.

Abstract: A system may include a control circuit and a multi-level power converter comprising a plurality of switches and a power inductor electrically coupled to the plurality of switches, wherein the power inductor is coupled to a switching node of the multi-level power converter, wherein the multi-level power converter is capable of applying three or more switching voltages to the switching node. The control circuit may generate control signals that define a sequence of switching of the plurality of switches of the power converter, the control circuit configured to, during a switching cycle of the converter in which the power inductor is magnetized and demagnetized, control switching of the plurality of switches among at least three switch configurations during magnetization and demagnetization of the power inductor such that a voltage on the switching node experiences a different respective magnitude of voltage in each of the at least three switch configurations.

Abstract: An amplifier circuit may include a first gain stage configured to receive an input signal at the first gain stage input and apply a first gain to the input signal to generate a first gain stage output signal at the first gain stage output, a second gain stage configured to receive the first gain stage output signal at the second gain stage input and apply a second gain to the first gain stage output signal to generate a second gain stage output signal at the second gain stage output, a feedforward gain stage configured to receive the input signal at the feedforward gain stage input and apply a feedforward gain to the input signal to generate a feedforward gain stage output signal at the feedforward gain stage output, and a compensation network coupled between the first gain stage output and the feedforward gain stage output.

Abstract: In accordance with embodiments of the present disclosure, a power converter system may comprise a plurality of power converter stages in a cascaded arrangement, the power converter stages comprising at least a first power converter stage and a second power converter stage configured to modify an operational state and/or an operational mode of the second power converter stage responsive to feedforward information associated with the first power converter stage.

Abstract: This application relates to methods and apparatus for driving a transducer with switching drivers. A driver circuit has first and second switching drivers for driving the transducer in a bridge-tied-load configuration, each of the switching drivers having a respective output stage for controllably switching the respective driver output node between high and low switching voltages with a controlled duty cycle. Each of switching drivers is operable in a plurality of different driver modes, wherein the switching voltages are different in said different driver modes. A controller controls the driver mode of operation and the duty cycle of the switching drivers based on the input signal. The controller is configured to control the duty cycles of the first and second switching drivers within defined minimum and maximum limits of duty cycles; and to transition between driver modes of operation when the duty cycle of one of the switching drivers reaches a duty cycle limit.

Abstract: Switched capacitor power converter circuitry configured to receive an input voltage and to output an output voltage, the switched capacitor power converter circuitry comprising: a switch network; a flying capacitor coupled to the switch network; and an output capacitor coupled to an output node of the switch network, wherein the switched capacitor power converter circuitry is operable in: a first mode in which the switch network operates at a fixed duty cycle; and a second mode in which the switch network operates at a variable duty cycle based on a predetermined flying capacitor charging threshold and a predetermined flying capacitor discharging threshold.

Abstract: A system for performing a measurement on a component, the system comprising: an integrated circuit (IC) comprising: analog to digital (ADC) converter circuitry; and processing circuitry, wherein the system further comprises: difference circuitry, wherein: the difference circuitry is operable to generate a compensated measurement voltage by subtracting a compensation voltage received from a voltage source external to the integrated circuit from a measurement voltage output by the component in response to a stimulus signal received by the component; the ADC circuitry is configured to convert the compensated measurement voltage into a digital compensated measurement signal; and the measurement circuitry is configured to generate a measurement result based on the digital compensated measurement signal.

Abstract: A force sensing system for determining if a user input has occurred, the system comprising: an input channel, to receive an input from at least one force sensor; an activity detection stage, to monitor an activity level of the input from the at least one force sensor and, responsive to an activity level which may be indicative of a user input being reached, to generate an indication that an activity has occurred at the force sensor; and an event detection stage to receive said indication, and to determine if a user input has occurred based on the received input from the at least one force sensor.

Abstract: A method of cough detection in a headset, the method comprising: receiving a first signal from an external transducer of the headset; receiving a second signal from an in-ear transducer of the headset; and detecting a cough of a user of the headset based on the first and second signals.

Abstract: In an example there is provided circuitry for detecting a type of accessory connected to a first jack plug inserted into a first jack port. The circuitry is configured to determine whether an audio signal is present at the tip or the ring of the first jack plug. If there is an audio signal present at the tip or the ring of the first jack plug, then the circuitry is configured to determine that the type of accessory is a stereo line-in accessory connected to a 3-pole jack plug.

Abstract: This disclosure relates to instrumenting of integrated circuits, and particularly with providing synchronized time stamps for logging data from multiple components. An example method includes injecting code in a read only memory (ROM) that performs the logging with time stamps. The method may include receiving, from a first component, data describing a first event with a first time stamp synchronized to a global clock; receiving, from a second component, data describing a second event with a second time stamp synchronized to the global clock; and generating a report comprising the first event and the second event, wherein the first event is synchronized with the second event. Other aspects are also disclosed.

Abstract: A power converter for converting an input voltage at an input of the power converter into an output voltage at an output of the power converter may include a first power converter branch comprising a first capacitor, a first switch network, and a first inductor, the first switch network arranged to selectably couple the first capacitor between an input voltage, a first reference voltage, and a first terminal of the first inductor, wherein a second terminal of the first inductor is coupled to an output node; a second power converter branch comprising a second capacitor, a second switch network, and a second inductor, the second switch network arranged to selectably couple the second capacitor between the input voltage, a second reference voltage, and a first terminal of the second inductor, wherein a second terminal of the second inductor is coupled to the output node; and a third switch network between the first power converter branch and the second power converter branch, wherein the third switch network is

Abstract: Noise cancellation operations consume battery power, and thus techniques for reducing power consumption by performing power management in active noise cancellation in consumer devices are beneficial for the user. One example power management technique described according to embodiments of this disclosure allow wind noise detection to switch between a high-power higher-accuracy operation and a low-power lower-accuracy operation. For example, multiple microphones may be available on the personal device for detecting wind noise, in which using multiple microphones increases accuracy but also increases battery consumption. A personal device may switch between using a single microphone and multiple microphones based on environmental conditions to provide improved performance in certain environmental conditions and reduced power consumption in other environmental conditions.

Abstract: Switched capacitor power converter circuitry comprising: a first converter fragment; a second converter fragment; and control circuitry, wherein the control circuitry is configured to selectively activate the second converter fragment based on an operating parameter indicative of a load current that the switched capacitor power converter circuitry is required to support.

Abstract: Circuitry for driving first and second loads, the circuitry comprising: a first output signal path for supplying a first driving signal to the first load; a second output signal path for supplying a second driving signal to the second load; sequencer circuitry configured to initiate a first state change in the first output signal path and a second state change in the second output signal path, wherein the sequencer circuitry is configured to control the initiation of the first and second state changes such that the second state change is not synchronised with the first state change.

Abstract: A method of equalising a signal derived from an input device, the method comprising: receiving the signal; applying an order-statistic filter to the signal in the frequency domain to generate a statistically filtered signal; equalising the received signal based on the statistically filtered signal to generate an equalised signal.

Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the a plurality of capacitor networks has a plurality of sampling capacitors for sampling over a plurality of sampling sub-phases an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC comprising a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

Abstract: A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.

Abstract: A system may include a pulse-width modulation mode path configured to drive a load at an output of the system in a first mode of operation, a linear mode path configured to drive the load in a second mode of operation, a common mode control feedback loop configured to set a value of a common mode output signal at the output in the second mode of operation, and an auxiliary circuit coupled to the common mode feedback control loop and configured to maintain a state of the common mode feedback control loop during the first mode of operation as the state was or will be during the second mode of operation.