Abstract: A magnetic disc storage system employing two stage actuators for simultaneously positioning recording heads over the top and bottom surfaces of the disc is disclosed. The recording heads are fastened to a distal end of respective top and bottom load beams. A base end of the load beams is connected to a voice coil motor (VCM) rotary actuator which simultaneously positions both recording heads over the disc. A silicon microactuator is also fastened to the distal end of at least one of the load beams for positioning the recording heads independent of one another, thereby allowing simultaneous tracking of embedded servo data. Various data formats are provided, including interleaving logical sector numbers, symbols of a logical sector, and segments of a logical sector, between the top and bottom physical sectors of a track.

Abstract: In a graphics card of a computer, a circuit is provided for displaying graphic presentations generated by the card on an external TV set. A TV adapter controls a horizontal state machine of a CRT controller so as to delay generation of CRT timing signals by a time period variable with horizontal lines. As a result, a composite video signal is provided with a time-base variable front porch to simulate VTR video signals. In response to the generated composite video signal, the TV set switches into a VTR mode to disable a comb filter used for separating luminance and chrominance components of a broadcast television signal.

Abstract: A system of ISA bus cards compatible with plug and play protocol stores common resource data in a plurality of programmable read only memories which are each installed on the individual bus cards. A random access memory is also provided on each one of the bus cards. In order to comply with the plug and play protocol, each of the random access memories is programmed independently from the read only memories with a unique identification that identifies the individual bus card. The separation of the storage location of the unique identification from the resource data common to all of the bus cards allows for mass production and programming of the read only memories, while still providing the unique identification for each bus card that is required by the plug and play protocol.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems which asynchronously samples an analog read signal, adaptively equalizes the resulting discrete time sample values according to a target partial response, extracts synchronous sample values through interpolated timing recovery, and detects digital data from the synchronous sample values using a Viterbi sequence detector. To increase the speed of the read channel, the FIR filters in the equalizer and interpolator are implemented according to a residue number system. Further, the residue number system implementation of the FIR filters uses "one-hot" encoding to decrease power dissipation.

Abstract: Short-circuit current and power consumption for an integrated circuit may be calculated by measuring short-circuit current for various cells within an integrated circuit using a Verilog.TM. logic level model of the cell. Each cell within an integrated circuit may be characterized by its inputs and outputs and connectivity. A corresponding SPICE sub-circuit model having the same logic characteristics as the cell may be generated. A number of calculation passes are made for each sub-circuit within a cell to determine short circuit current for each sub-circuit at various signal rise and fall times and for various inputs and outputs. Current data may be stored in a format compatible with Verilog.TM. propagation delay data. Overall power consumption and short circuit current for an integrated circuit may then be calculated from Verilog.TM. logic model data. The use of the Verilog.TM. model eliminates the need to calculate short circuit current at a SPICE circuit level.

Abstract: An input circuit to a semiconductor device may selectively accept different voltage logic levels (e.g., TTL or CMOS) as selected by a preset selection signal. The selection signal activates an N-type or P-type transistor in the input circuit which alters the threshold switching voltage of the input circuit logic. By altering the input threshold voltage, both TTL and CMOS input signals may be correctly triggered. An additional circuitry may be provided to allow a low voltage circuit (e.g., 3.3 Volts) to be tolerant of higher voltage inputs (e.g., 5 Volts). An isolation transistor isolates the input of the circuit from the high voltage signal, while a pulldown transistor pulls a high logic, high voltage signal down to supply voltage level.

Abstract: The display controller of the present invention reduces power consumption by suppressing clock signals to a display memory (comprising SGRAM or SDRAM) between screen refreshes and memory accesses. The present invention takes advantage of power-down modes provided for SGRAM and/or SDRAM memories which are used in the prior art to place a memory in an active suspend mode. Further energy savings are realized and memory bandwidth increased when using a display memory comprising two banks. When one bank of memory is being accessed, the other bank of memory is precharged and activated. Succeeding pages of memory are placed in alternate banks of display memory. Thus, then data is to be accessed from a next page of memory, the corresponding bank is already charged and ready to be accessed.

Abstract: A network controller has a default non-DMA mode of data transfer that transfers received data frames to a desired location in internal memory under control of a host CPU. A DMA mode of data transfer is engaged to transfer accumulated data frames via a DMA controller to system memory when the host CPU is not available to handle the frame processing. An automatic switch back mechanism is provided to allow the network controller to automatically switch back to the non-DMA data transfer mode as soon as the host CPU is able to return to processing of received frames.

Abstract: A mechanism to allow dynamic configurations and/or diagnostic of a computer system from a remote location is provided. The computer system receives instruction codes of a program from a data source. When executed by the CPU, the instruction codes performs the necessary erase and program operations to embed a firmware program onto to the flash memory. The firmware program can be used for configurations or diagnostic purpose.

Abstract: Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite-field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

Abstract: A disc drive storage system having a plurality of data tracks and data sectors within each track, wherein each track further comprises a redundancy sector for reconstructing a data sector unrecoverable at the sector level. The latency of the storage system is minimized by generating track level redundancy data over the write range of data sectors and storing the "write" redundancy to the redundancy sector. Then during idle time of the storage system, the track level redundancy is regenerated for the entire track. If an unrecoverable data sector is encountered during the idle time redundancy regeneration, and the unrecoverable data sector is within the write range of the previous write operation, then it is reconstructed using the track level redundancy data stored in the redundancy sector.

Abstract: The apparatus of the present invention includes a frame for attaching the clamp of a hand test socket to a workpress assembly of a high-speed IC handler. The frame attaches to a workpress assembly. Utilizing the clamp of a test socket recycles frequently unused test socket parts and eliminates the need for custom fabricated workpress assembly components. The method for adapting the hand test socket for use on the workpress assembly includes the steps: providing a test socket having a base and a top cover, the top cover including a clamp; removing the top cover and the clamp; configuring the clamp for use in a workpress assembly; and attaching the clamp to the workpress assembly.

Abstract: A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which descriptors of data buffers are stored in a circular descriptor queue. The descriptors of those data buffers that are currently available for use in a DMA transfer are maintained in contiguous locations in the descriptor queue. The location of the first available descriptor and the number of currently available descriptors in the descriptor queue are provided to a network controller. Based on this information, the network controller then obtains a set of available descriptors and fills the corresponding buffers with data as it arrives on the different channels. When the use of a data buffer in a DMA transfer is complete, the descriptor for this buffer is made available again in the descriptor queue by re-filling this descriptor immediately following the available descriptors.

Abstract: A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To increase the throughput of the read channel, multiple sample values are processed in parallel. In the example embodiment disclosed herein, two sample values are processed in parallel.

Abstract: A bi-directional data pipeline for interfacing a memory with a communications port includes a series of four pipeline elements comprising two DMA buffers and first and second holding registers. A data word is transferred from memory to the DMA buffers, each holding one data byte of the data word. With each clock cycle, the data bytes are successively transferred through the two holding registers. Two comparators are used to determine if three successive identical data bytes are present in the pipeline. If three identical bytes are detected, run length encoding is enabled, and a run length count register is incremented for each successive identical byte received through the pipeline. The run length count and associated data byte are transferred to a FIFO for transmission over the data path. A tag associated with the run length count distinguishes the run length count from data bytes in the FIFO.

Abstract: In storage subsystems such as winchester disk, blocks of sequential data corresponding to sectors are concurrently accessed by the disk and the host. Semiconductor memory devices for storing block data are often utilized as storage location for sectors of data read or written to the disk and the host. Application of a semiconductor memory which increases the effective transfer rate of the system is highly desirable particularly in disk storage systems. A semiconductor memory for use in disk storage applications where information is transferred in blocks of data is hereby disclosed. Specifically, the memory includes a main memory configured as a random access memory array having rows and columns, each row having a plurality of n-bit words, a secondary memory having a data register file, first and second parallel-by-bit interfaces and a transferring circuit for transferring data between the main and secondary memories.

Abstract: A signal detector for detecting the presence of a intermittent signal component in a signal. The signal detector receives each of the signal strength samples during a corresponding iteration, and compares a threshold value with the received signal sample. The signal detector sets a counter to a pre-determined number if the sample compared is greater than the threshold value. The signal detector decrements the persistence counter if a corresponding sample is not greater than the threshold value. If the persistence counter is greater than a trigger value, the detector indicates the presence of a intermittent signal component or otherwise declares the absence of a intermittent signal component. The detector may indicate the presence of a intermittent signal component by a logical value of 1 and the absence by a logical value of 0. The threshold value is composed of two components; the intermittent signal component and the background signal component.

Abstract: A keyboard controller is used to drive the PDEN pins on DIMMs. A PC has a keyboard controller with a plurality of programmable input/output (I/O) pins. The state of the programmable I/O pins can be set by software. The pins are coupled to individual PDEN pins on the DIMMs. When the programmable I/O pins are activated, the PDEN pins are driven active and each DIMM outputs a signal indicating its characteristics. The signals are latched and stored for use by a memory controller.

Abstract: A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

Abstract: This invention provides apparatus for reliably and efficiently reading data from a magnetic storage medium under the condition that adjacent magnetization regions are partially erased. A simplified nonlinear description of a read signal resulting from such partially erased magnetization regions is used to derive a state machine model of the read signal. The state machine model implicitly defines a sequence detector for demodulating recorded data from received samples. For a PR4 signal, the state machine has ten states; for an EPR4 signal, the state machine has eighteen states; and for an EEPR4 signal, the state machine has twenty-six states. The PR4 machine is further simplified using squaring and state sharing to provide state machine models with six and four states.