Abstract: A system and method is provided for image sensing. The image sensing system includes a comparator for comparing an input signal representing a sensed light signal from at least one pixel of the image sensing system and a reference signal. The comparator includes at least one digital transistor.

Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

Abstract: An image sensor including at least one pixel for collecting charge in its photodiode is provided. The image sensor comprises: a substrate having a first surface on a front side and a second surface on a back side, a photodetector formed in the silicon substrate and having a light-receiving surface on the second surface, and a first layer with positive charges disposed on the second surface, the first layer being configured to form an electron accumulation region at the light-receiving surface of the photodetector for suppressing a dark current at a back side interface of the image sensor. A method for fabricating an image sensor including a first layer with positive charges is also provided.

Abstract: The invention provides a voltage regulator with multiple output ranges. The voltage regulator includes a voltage divider that has at least a first resistor and a second resistor. The resistance ratio of the first resistor to the second resistor is 1:(X?1). The input of the regulator is connected to the first resistor, and the output is connected to the second resistor. A voltage source may provide a reference voltage Vref to a connecting point between the first resistor and the second resistor. At least one working circuit is connected to the output to provide the output voltage as Vout=Vin?X(Vin?Vref), wherein Vin is the input voltage. As another option, the at least one working circuit may be deactivated and the output may be coupled to ground.

Abstract: An image sensor includes at least a first row and a second row of photodiodes, each photodiode being coupled with an associated transistor, each associated transistor including a gate, the first and second row of photodiodes forming a series of 2×2 Bayer-pattern units. In each Bayer-pattern unit, a first photodiode and a second photodiode in the first row are designated respectively as a first green pixel and a blue pixel, and a third photodiode and a fourth photodiode in the second row are designated respectively as a red pixel and a second green pixel, wherein a position of the gate of the transistor associated with the first photodiode relative to the first photodiode and a position of the gate of the transistor associated with the fourth photodiode relative to the fourth photodiode are the same.

Abstract: The present invention relates to an integrated circuit having a flexible reference. In an example, the integrated circuit includes a reference generator, and the reference generator can generate a flexible reference signal in response to a control signal. The flexible reference signal can be changed freely by adjusting the control signal. By providing the flexible reference, the present invention can enhance the capability of verification and characterization for an integrated circuit design and reduce the physical layout area of the integrated circuit design. The present invention also relates to a method of operating the integrated circuit with a flexible reference signal.

Abstract: The present invention provides a compact row decoder with multiple voltage support. The row decoder may include a global driver and a plurality of row-level drivers. The global driver may include one or more voltage level shifters that are operable to provide multiple voltages required to drive each of the plurality of row-level drivers. The plurality of row-level drivers each may include only one voltage level shifter. In an example, the row-level driver includes an address decoder implemented in a digital domain providing an address selection signal, a voltage level shifter to convert the address selection signal to an analog domain, and a row driver receiving driving signals from the global driver. The row driver has no voltage level shifter contained therein. Thus, the row-level drivers and the row decoder may be very compact. The present invention further provides a CMOS image sensor including the row decoder and a method of operating the CMOS image sensor.

Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.

Abstract: The present invention relates to a single chip image sensor with both visible light image and ultraviolet light detection ability and methods to implement the single chip image sensor. In an embodiment, a single chip image sensor may comprise a first plurality of sensor cells provided on a substrate, the first plurality of sensor cells each including a photo detector sensitive to visible light, and a UV coating layer provided for the first plurality of sensor cells to convert incident UV light to visible light.

Abstract: The present application relates to a multimedia data capture and processing (C&P) device. In an example, the multimedia data C&P device comprises a multimedia sensor configured to capture a first multimedia data; and a device processor configured to obtain a preset information, and generate a second multimedia data according to the first multimedia data and the preset information, at least a part of the second multimedia data presenting the preset information. The present application also relates to a user terminal and multimedia data processing server.

Abstract: The present invention provides a compact row decoder with multiple voltage support. The row decoder may include a global driver and a plurality of row-level drivers. The global driver may include one or more voltage level shifters that are operable to provide multiple voltages required to drive each of the plurality of row-level drivers. The plurality of row-level drivers each may include only one voltage level shifter. In an example, the row-level driver includes an address decoder implemented in a digital domain providing an address selection signal, a voltage level shifter to convert the address selection signal to an analog domain, and a tow driver receiving driving signals from the global driver. The row driver has no voltage level shifter contained therein. Thus, the row-level drivers and the row decoder may be very compact. The present invention further provides a CMOS image sensor including the row decoder and a method of operating the CMOS image sensor.

Abstract: The present invention relates to an integrated circuit having a flexible reference. In an example, the integrated circuit includes a reference generator, and the reference generator can generate a flexible reference signal in response to a control signal. The flexible reference signal can be changed freely by adjusting the control signal. By providing the flexible reference, the present invention can enhance the capability of verification and characterization for an integrated circuit design and reduce the physical layout area of the integrated circuit design.

Abstract: The invention provides a voltage regulator with multiple output ranges. The voltage regulator includes a voltage divider that has at least a first resistor and a second resistor. The resistance ratio of the first resistor to the second resistor is 1:(X?1). The input of the regulator is connected to the first resistor, and the output is connected to the second resistor. A voltage source may provide a reference voltage Vref to a connecting point between the first resistor and the second resistor. At least one working circuit is connected to the output to provide the output voltage as Vout=Vin?X(Vin?Vref), wherein Vin is the input voltage. As another option, the at least one working circuit may be deactivated and the output may be coupled to ground.