Patents Assigned to Clearspeed Solutions Limited
  • Clock distribution system
    Patent number: 7290162
    Abstract: A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a, 14b, 14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: October 30, 2007
    Assignee: Clearspeed Solutions Limited
    Inventors: Ian Swarbrick, David Williams