Patents Assigned to CMK Corporation
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Patent number: 8035979Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.Type: GrantFiled: December 13, 2010Date of Patent: October 11, 2011Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
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Publication number: 20110090657Abstract: A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.Type: ApplicationFiled: December 13, 2010Publication date: April 21, 2011Applicants: CMK CORPORATION, RENESAS EASTERN JAPAN SEMICONDUCTOR INC.Inventors: Yutaka YOSHINO, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
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Patent number: 7910405Abstract: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the semiconductor constructing body. An adhesion increasing film is formed between the insulating layer, and at least one of the semiconductor constructing body and the base member around the semiconductor constructing body, for preventing peeling between the insulating layer and the at least one of the semiconductor constructing body and base member.Type: GrantFiled: June 12, 2007Date of Patent: March 22, 2011Assignees: Casio Computer Co., Ltd., CMK CorporationInventors: Osamu Okada, Hiroyasu Jobetto
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Patent number: 7894200Abstract: The present invention provides a printed wiring board with a built-in semiconductor element in which an insufficient or excessive amount of filled sealing material does not affect excellent adhesion of the printed wiring board to an overlying wiring board. The printed wiring board with a built-in semiconductor element comprises a built-in semiconductor element, in which at least the lower surface, the upper surface, or the side surface of the semiconductor element is covered with an insulating film, and an insulating layer is provided in the side and upper portions of the semiconductor element.Type: GrantFiled: November 28, 2006Date of Patent: February 22, 2011Assignees: CMK Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Yutaka Yoshino, Takahiro Shirai, Shinji Kadono, Mineo Kawamoto, Minoru Enomoto, Masakatsu Goto, Makoto Araki, Naoki Toda
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Patent number: 7867828Abstract: A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.Type: GrantFiled: July 24, 2007Date of Patent: January 11, 2011Assignees: Casio Computer Co., Ltd., CMK CorporationInventor: Hiroyasu Jobetto
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Patent number: 7709942Abstract: A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around the semiconductor constructing body, upper interconnections which are formed on the insulating layer and each includes at least one interconnection layer, at least some of the upper interconnections are connected to the external connection electrodes of the semiconductor constructing body, lower interconnections which are formed on the other surface of the base plate and each includes at least one interconnection layer, and at least some of the lower interconnections which are electrically connected to the upper interconnections.Type: GrantFiled: June 2, 2004Date of Patent: May 4, 2010Assignees: Casio Computer Co., Ltd., CMK CorporationInventor: Hiroyasu Jobetto
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Patent number: 7615411Abstract: A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around the semiconductor constructing body, upper interconnections which are formed on the insulating layer and each includes at least one interconnection layer, at least some of the upper interconnections are connected to the external connection electrodes of the semiconductor constructing body, lower interconnections which are formed on the other surface of the base plate and each includes at least one interconnection layer, and at least some of the lower interconnections which are electrically connected to the upper interconnections.Type: GrantFiled: March 12, 2008Date of Patent: November 10, 2009Assignees: Casio Computer Co., Ltd., CMK CorporationInventor: Hiroyasu Jobetto
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Patent number: 7608480Abstract: A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body and has a thickness substantially equal to the semiconductor constructing body. An one upper interconnecting layer is provided on the semiconductor constructing body and insulating layer, and electrically connected to the external connection electrodes. A vertical conducting portion extends through the insulating layer and electrically connects the metal foil and upper interconnecting layer.Type: GrantFiled: July 20, 2007Date of Patent: October 27, 2009Assignees: Casio Computer Co., Ltd., CMK CorporationInventor: Hiroyasu Jobetto
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Patent number: 7489032Abstract: A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.Type: GrantFiled: December 20, 2004Date of Patent: February 10, 2009Assignees: Casio Computer Co., Ltd., CMK CorporationInventor: Hiroyasu Jobetto
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Patent number: 7445964Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.Type: GrantFiled: December 13, 2006Date of Patent: November 4, 2008Assignees: Casio Computer Co., Ltd., CMK CorporationInventors: Ichiro Mihara, Takeshi Wakabayashi, Toshihiro Kido, Hiroyasu Jobetto, Yutaka Yoshino, Nobuyuki Kageyama, Daita Kohno, Jun Yoshizawa
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Patent number: 7363706Abstract: This invention provides a multilayer printed wiring board having flat via holes. This is a multilayer printed wiring board formed by alternately laminating multiple metal foils and insulating layers, in which an interlayer connection via pad provided in a first insulating layer, a wiring circuit and an interlayer connection via bottom pad of a second insulating layer are provided in the same surface layer and at least the interlayer connection via pad and the interlayer connection via bottom pad of the second insulating layer have the same thickness.Type: GrantFiled: August 25, 2005Date of Patent: April 29, 2008Assignee: CMK CorporationInventor: Eiji Hirata
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Publication number: 20080014681Abstract: A semiconductor device includes a base plate, and a semiconductor constituent body formed on the base plate. The semiconductor constituent body has a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constituent body. A hard sheet is formed on the insulating layer. An interconnection is connected to the external connecting electrodes of the semiconductor constituent body.Type: ApplicationFiled: July 24, 2007Publication date: January 17, 2008Applicants: Casio Computer Co., Ltd., CMK CORPORATIONInventor: Hiroyasu JOBETTO
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Publication number: 20070264754Abstract: A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body and has a thickness substantially equal to the semiconductor constructing body. An one upper interconnecting layer is provided on the semiconductor constructing body and insulating layer, and electrically connected to the external connection electrodes. A vertical conducting portion extends through the insulating layer and electrically connects the metal foil and upper interconnecting layer.Type: ApplicationFiled: July 20, 2007Publication date: November 15, 2007Applicants: CASIO COMPUTER CO., LTD., CMK CORPORATIONInventor: Hiroyasu Jobetto
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Patent number: 7279750Abstract: A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body and has a thickness substantially equal to the semiconductor constructing body. An one upper interconnecting layer is provided on the semiconductor constructing body and insulating layer, and electrically connected to the external connection electrodes. A vertical conducting portion extends through the insulating layer and electrically connects the metal foil and upper interconnecting layer.Type: GrantFiled: March 30, 2005Date of Patent: October 9, 2007Assignees: Casio Computer Co., Ltd., CMK CorporationInventor: Hiroyasu Jobetto
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Publication number: 20070232061Abstract: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the semiconductor constructing body. An adhesion increasing film is formed between the insulating layer, and at least one of the semiconductor constructing body and the base member around the semiconductor constructing body, for preventing peeling between the insulating layer and the at least one of the semiconductor constructing body and base member.Type: ApplicationFiled: June 12, 2007Publication date: October 4, 2007Applicants: Casio Computer Co., Ltd., CMK CORPORATIONInventors: Osamu Okada, Hiriyasu Jobetto
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Patent number: 7243425Abstract: The present invention provides a printed wiring board in which there is no positional deviation between a blind via hole and a land and which enables high-density wiring design to be easily achieved. Provided is a method of manufacturing a printed wiring board in which wiring pattern forming layers are connected by a blind via hole, which includes the steps of forming a wiring pattern by etching at least metal foil laminated on a surface of an insulating layer and forming a land having a window portion in a portion where a blind via hole is to be formed; irradiating the window portion with a laser beam having a diameter larger than the diameter of the window portion but smaller than the diameter of the land, thereby making a nonthrough hole for forming the blind via hole; and forming a blind via hole by forming a plating on the nonthrough hole and the land.Type: GrantFiled: August 25, 2005Date of Patent: July 17, 2007Assignee: CMK CorporationInventor: Eiji Hirata
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Publication number: 20070099409Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.Type: ApplicationFiled: December 13, 2006Publication date: May 3, 2007Applicants: Casio Computer Co., Ltd., CMK CorporationInventors: Ichiro Mihara, Takeshi Wakabayashi, Toshihiro Kido, Hiroyasu Jobetto, Yutaka Yoshino, Nobuyuki Kageyama, Daita Kohno, Jun Yoshizawa
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Publication number: 20070074902Abstract: The present invention provides a printed-wiring board which can make the electric wiring densified and can be thinned, even when having a BVH of a non-penetration hole filled with a selectively plating, formed therein for interfacial connection means. The printed-wiring board has a blind via hole connecting different wiring-pattern-formed layers with each other, wherein the blind via hole is a non-penetration hole filled with a plating, and the plating is not formed on a wiring pattern including the round of the blind via hole.Type: ApplicationFiled: June 14, 2006Publication date: April 5, 2007Applicant: CMK CORPORATIONInventor: Eiji Hirata
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Patent number: 7183639Abstract: A semiconductor device includes at least one semiconductor structure which has a plurality of external connection electrodes formed on a semiconductor substrate. An insulating sheet member is arranged on the side of the semiconductor structure. Upper interconnections have connection pad portions that are arranged on the insulating sheet member in correspondence with the upper interconnections and connected to the external connection electrodes of the semiconductor structure.Type: GrantFiled: August 12, 2004Date of Patent: February 27, 2007Assignees: Casio Computer Co., Ltd., CMK CorporationInventors: Ichiro Mihara, Takeshi Wakabayashi, Toshihiro Kido, Hiroyasu Jobetto, Yutaka Yoshino, Nobuyuki Kageyama, Daita Kohno, Jun Yoshizawa
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Patent number: 7087845Abstract: The present invention is characterized in that in a metal-core multilayer printed wiring board (1) which is obtained by forming one or more of at least inner layers of a laminate having a insulating layer and a conductor layer stacked alternately from a metal plate and has the metal plate as a core, the metal plate (13) is disposed below a site on which a heating element (10) is to be mounted, a surface layer over which the heating element (10) is to be mounted is connected to the metal plate (13) of the inner layer via a BVH (12) and a heat radiation layer (14) is formed over the surface layer. The present invention makes it possible to efficiently radiate heat, which has been released from the heating element, to the outside of the printed wiring board without impairing the packaging density of circuits and at the same time, to mount another element on the side opposite to the side on which the heating element exists.Type: GrantFiled: January 28, 2004Date of Patent: August 8, 2006Assignees: CMK Corporation, Advics Co., Ltd.Inventors: Hiroshi Tohkairin, Kenji Sakakibara, Hideki Kabune