Patents Assigned to CNEX LABS
  • Patent number: 11494254
    Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, determine which threshold adjustment range has been activated by reading a 1 and 0 counter, select an adjusted read threshold, based on the threshold adjustment range, to reread the user data in a physical block using the adjusted read threshold to correct the user data; and reading the user data in the physical block using the adjusted read threshold selected from the threshold adjustment range.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: November 8, 2022
    Assignee: CNEX LABS, Inc.
    Inventors: Jun Tao, Chih-Chieng Cheng, Shanying Luo
  • Patent number: 10915399
    Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, detect an uncorrectable error in the user data, detect a sector balanced when the number of 1's and 0's in the user data is within the difference stored in a range register, apply an XOR RAID recovery to correct the uncorrectable error in the user data; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured to forego an additional read of a sector N with a different value of the read threshold when the sector balanced initiates the XOR RAID recovery.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: February 9, 2021
    Assignee: CNEX LABS, Inc.
    Inventors: Jun Tao, Chih-Chieng Cheng, Bo Jiang, Shanying Luo
  • Patent number: 10740176
    Abstract: A computing system includes: a control circuit for determining a user data, generating a base set including a base protection data based on encoding the user data, calculating an extra protection data based on encoding the base set; and a storage circuit for storing the extra protection data (210) corresponding to the base set. The computing system can further include: an storage circuit for providing a received codeword corresponding to a user data and a base protection data, providing an extra protection data corresponding to the received codeword; and a control circuit for calculating a base syndrome from the received codeword, calculating a further syndrome from the extra protection data, and decoding the received codeword to recover the user data, the base protection data, or a combination thereof using the base syndrome and the further syndrome.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 11, 2020
    Assignee: CNEX LABS, Inc.
    Inventors: Xiaojie Zhang, Pengfei Huang
  • Patent number: 10713104
    Abstract: A storage system includes: a control processor, configured to: read user data, generate a bit flip array from the user data including limiting a threshold offset range, and select an optimal read threshold set from the bit flip array; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured read a sector N with the optimal read threshold set for enhancing performance of the non-volatile memory array.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: July 14, 2020
    Assignee: CNEX LABS, Inc.
    Inventors: Xiaojie Zhang, Yi Liu
  • Patent number: 10678662
    Abstract: A computing system includes: a data block including a data; a storage engine, coupled to the data block, configured to process data, as hard information or soft information, through channels including a failed channel and a remaining channel, calculate an aggregated output from a hard decision from the remaining channel, calculate a selected magnitude from a magnitude from the remaining channel with an error detected, calculate an extrinsic soft information based on the aggregated output and the selected magnitude, and decode the failed channel with a scaled soft metric based on the extrinsic soft information.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: June 9, 2020
    Assignee: CNEX LABS, Inc.
    Inventor: Xiaojie Zhang
  • Patent number: 10558524
    Abstract: A computing system includes an array of storage devices configured to store storage data and check data; and a storage engine, coupled to the array of storage devices, configured to: access the storage data, detect an erasure storage data, an erasure check data, or a combination thereof when the storage data is not accessible from the array of storage devices, and recover the storage data from the erasure storage data, the erasure check data, or the combination thereof by applying at least one of a block of check data including a slope from the check data.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 11, 2020
    Assignee: CNEX LABS, Inc.
    Inventors: Bing Fan, Xiaojie Zhang
  • Patent number: 10558523
    Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: February 11, 2020
    Assignee: CNEX LABS, Inc.
    Inventors: Alan Armstrong, Yiren Ronnie Huang, Xiaojie Zhang
  • Patent number: 10503679
    Abstract: A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 10, 2019
    Assignee: CNEX LABS, INC.
    Inventor: Yiren Ronnie Huang
  • Patent number: 10417090
    Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed with the first protection and the second protection.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: September 17, 2019
    Assignee: CNEX LABS, Inc.
    Inventors: Alan Armstrong, Patrick Lee, Yiren Ronnie Huang
  • Patent number: 10402595
    Abstract: A computing system includes: an interface circuit configured to provide access to a data block including an arrangement of multiple individual data; and a processing circuit, coupled to the interface circuit, configured to generate a non-orthogonal protection data corresponding to instances of the individual data along a non-orthogonal direction within the data block for correcting the one or more of the corresponding instances of the individual data.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 3, 2019
    Assignee: CNEX LABS, Inc.
    Inventors: Alan Armstrong, Yiren Ronnie Huang, Xiaojie Zhang
  • Patent number: 10394651
    Abstract: A computing system includes an array of storage devices configured to provide access to storage data and check data corresponding to a data block length; and a storage engine, coupled to the array of storage devices, configured to: detect one more erroneous data, one more erroneous check data, or a combination thereof for representing the storage data, the check data, or a combination thereof inaccessible or failing a status check process after initial storage thereof, determine a prime shift factor for representing a smallest prime number not less than a block unit-quantity, wherein the block unit-quantity is for representing a quantity of shift units within the data block length, and iteratively generate a target recovery set based on a circular-shift mechanism utilizing the prime shift factor for recovering the one more erroneous data, the one more erroneous check data, or a combination thereof.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: August 27, 2019
    Assignee: CNEX LABS, Inc.
    Inventors: Xiaojie Zhang, Bing Fan
  • Patent number: 10331515
    Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages includes shifted parities generated, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed by selecting one of the shifted parities for the first protection and the second protection.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 25, 2019
    Assignee: CNEX LABS, Inc.
    Inventors: Alan Armstrong, Patrick Lee
  • Patent number: 10269422
    Abstract: A storage system includes: a control processor unit, configured to: initiate a read of a raw data page, having correctable errors, calculate a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculate a correction model characterization based on the RBER (EQ1); and a non-volatile storage array, coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 23, 2019
    Assignee: CNEX LABS, Inc.
    Inventor: Xiaojie Zhang
  • Patent number: 10114569
    Abstract: A computing system includes: a control circuit configured to: determine a user data, generate a base set including a base protection data based on encoding the user data according to a coding mechanism, generate an extra protection data based on encoding the user data differently from the base set according to the coding mechanism; and a storage circuit configured to store the extra protection data corresponding to the base set. The computing system can further include: an storage circuit configured to: provide a received codeword corresponding to a user data and a base protection data, provide an extra protection data corresponding to the received codeword; a control circuit configured to: decode the received codeword according to a coding mechanism, and further decode the received codeword to recover the user data based on decoding differently from decoding the base set and using the extra protection data according to the coding mechanism.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 30, 2018
    Assignee: CNEX LABS, Inc.
    Inventors: Yiren Ronnie Huang, Xiaojie Zhang
  • Patent number: 10063638
    Abstract: A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 28, 2018
    Assignee: CNEX LABS, INC.
    Inventor: Yiren Ronnie Huang
  • Patent number: 9898404
    Abstract: An improved garbage collection (“GC”) process configured to recover new blocks from used storage space is disclosed. After initiating the GC process for a flash memory in accordance with at least one of predefined triggering events, a first valid page within a first block marked as an erasable block is identified. Upon determining a first signature representing the content of the first valid page according to a predefined signature generator, the process identifies a second valid page within a second block as a duplicated page of the first valid page in response to the first signature. The process subsequently associates the logical block address (“LBA”) of the first valid page to the second valid page. In an alternative embodiment, page compression and sequential order of page arrangement can also be implemented to further enhance efficiency of garbage collection.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: February 20, 2018
    Assignee: CNEX LABS
    Inventors: Yiren Ronnie Huang, Aaron Huang