Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, determine which threshold adjustment range has been activated by reading a 1 and 0 counter, select an adjusted read threshold, based on the threshold adjustment range, to reread the user data in a physical block using the adjusted read threshold to correct the user data; and reading the user data in the physical block using the adjusted read threshold selected from the threshold adjustment range.

Abstract: A storage system includes: a control processor, configured to: read user data with a read threshold, detect an uncorrectable error in the user data, detect a sector balanced when the number of 1's and 0's in the user data is within the difference stored in a range register, apply an XOR RAID recovery to correct the uncorrectable error in the user data; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured to forego an additional read of a sector N with a different value of the read threshold when the sector balanced initiates the XOR RAID recovery.

Abstract: A computing system includes: a control circuit for determining a user data, generating a base set including a base protection data based on encoding the user data, calculating an extra protection data based on encoding the base set; and a storage circuit for storing the extra protection data (210) corresponding to the base set. The computing system can further include: an storage circuit for providing a received codeword corresponding to a user data and a base protection data, providing an extra protection data corresponding to the received codeword; and a control circuit for calculating a base syndrome from the received codeword, calculating a further syndrome from the extra protection data, and decoding the received codeword to recover the user data, the base protection data, or a combination thereof using the base syndrome and the further syndrome.

Abstract: A storage system includes: a control processor, configured to: read user data, generate a bit flip array from the user data including limiting a threshold offset range, and select an optimal read threshold set from the bit flip array; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured read a sector N with the optimal read threshold set for enhancing performance of the non-volatile memory array.

Abstract: A computing system includes: a data block including a data; a storage engine, coupled to the data block, configured to process data, as hard information or soft information, through channels including a failed channel and a remaining channel, calculate an aggregated output from a hard decision from the remaining channel, calculate a selected magnitude from a magnitude from the remaining channel with an error detected, calculate an extrinsic soft information based on the aggregated output and the selected magnitude, and decode the failed channel with a scaled soft metric based on the extrinsic soft information.

Abstract: One embodiment of the present invention capable of decommissioning a defective non-volatile memory (“NVM”) page in a block is disclosed. A process able to logically decommission a defective page is able to detect defective or bad pages while executing a write operation writing information to one or more NVM page in a NVM block. For example, after examining operation status after completion of the write operation, the NVM page is identified as a defective page if the operation status fails to meet a set of predefined conditions under a normal write operation. Upon marking a location of a page status table to indicate the NVM page as defective page, the page status table containing the page defective information associated with the NVM page is stored at a predefined page in the NVM block.

Abstract: A computing system includes an array of storage devices configured to store storage data and check data; and a storage engine, coupled to the array of storage devices, configured to: access the storage data, detect an erasure storage data, an erasure check data, or a combination thereof when the storage data is not accessible from the array of storage devices, and recover the storage data from the erasure storage data, the erasure check data, or the combination thereof by applying at least one of a block of check data including a slope from the check data.

Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.

Abstract: A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame.

Abstract: A method for processing a trim command via an input and output (“I/O”) command of a solid-state drive (“SSD”) using various tables is disclosed. The process is able to retrieve a trim node state table (“TNST”) from a local memory in response to the trim command. Upon identifying current node status of the TNST associated with a logical block address (“LBA”) referenced by the trim command, a trim operation is processed to a node if the current node status indicates a pending state. After changing the node status to a dirty state when the current node status is in a clean state, the content of a trim invalid bitmap table (“TIBT”) is updated to indicate the status of LBAs when the current node status is in a dirty state.

Abstract: The power protection system includes a host driver in the host system and an SSD driver situated in an SSD. In one aspect, the host driver includes a write buffer able to store information during a write operation to an open-channel solid state drive (“OCSSD”). The SSD driver connected to the host driver via a bus includes an SSD double data rate (“DDR”) buffer configured to store a copy of content similar to content in the write buffer and an SSD nonvolatile memory (“NVM”) coupled to the SSD DDR buffer and configured to preserve the data stored in the SSD DDR buffer when a power failure is detected. The SSD driver also includes a power supply, which can be a capacitor, coupled to the SSD DDR buffer for providing power to the SSD DDR buffer when the power is lost.

Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed with the first protection and the second protection.

Abstract: A computing system includes: an interface circuit configured to provide access to a data block including an arrangement of multiple individual data; and a processing circuit, coupled to the interface circuit, configured to generate a non-orthogonal protection data corresponding to instances of the individual data along a non-orthogonal direction within the data block for correcting the one or more of the corresponding instances of the individual data.

Abstract: A computing system includes an array of storage devices configured to provide access to storage data and check data corresponding to a data block length; and a storage engine, coupled to the array of storage devices, configured to: detect one more erroneous data, one more erroneous check data, or a combination thereof for representing the storage data, the check data, or a combination thereof inaccessible or failing a status check process after initial storage thereof, determine a prime shift factor for representing a smallest prime number not less than a block unit-quantity, wherein the block unit-quantity is for representing a quantity of shift units within the data block length, and iteratively generate a target recovery set based on a circular-shift mechanism utilizing the prime shift factor for recovering the one more erroneous data, the one more erroneous check data, or a combination thereof.

Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages includes shifted parities generated, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed by selecting one of the shifted parities for the first protection and the second protection.

Abstract: A system configuration containing a host, solid state drive (“SSD”), and controller able to perform a hybrid mode non-volatile memory (“NVM”) access is disclosed. Upon receiving a command with a logical block address (“LBA”) for accessing information stored in NVM, a secondary flash translation layer (“FTL”) index table is loaded to a first cache and entries in a third cache is searched to determine validity associated with stored FTL table. When the entries in the third cache are invalid, the FTL index table in the second cache is searched to identify valid FTL table entries. If the second cache contains invalid FTL index table, a new FTL index table is loaded from NVM to the second cache. The process subsequently loads at least a portion of FTL table indexed by the FTL index table in the third cache.

Abstract: A storage system includes: a control processor unit, configured to: initiate a read of a raw data page, having correctable errors, calculate a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculate a correction model characterization based on the RBER (EQ1); and a non-volatile storage array, coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.

Abstract: A storage system using dual error detection and repair (“EDR”) using a host memory buffer (“HMB”) is disclosed. In one aspect, the EDR can be CRC or ECC. The storage system is able to retrieve information from an SSD and reformatting the information into a data structure based on a host based a random-access memory (“RAM”) storage configuration. After designating a portion of RAM word for storing data and another portion of RAM word for storing data EDR, the data is organized according to the RAM word configuration with EDR. Upon generating transmission EDR according to a packet structure capable of carrying data for transmission, the system is configured to discard transmission EDR and stores the data with data EDR in the RAM inside of the host upon arrival from the SSD via a bus.

Abstract: One embodiment of the present invention discloses a process of low latency non-volatile memory access using various approaches. In one aspect, a process for low latency memory access to a non-volatile memory (“NVM”) of a solid state drive (“SSD”) is able to generate a submission queue entry (“SQE”) for an SSD memory access by a host to a connected SSD. Upon pushing the SQE from the host to a submission queue (“SQ”) viewable by a controller of the SSD, the counter value of an SQ header pointer is incremented to reflect storage of the first SQE in the SQ. After detecting the SQE in the SQ by a snooping component in the memory controller in accordance with the SQ header pointer, the SQE is fetched from the SQ by the controller and one or more SSD memory instructions are subsequently executed in response to content of the SQE.

Abstract: A computing system includes: a control circuit configured to: determine a user data, generate a base set including a base protection data based on encoding the user data according to a coding mechanism, generate an extra protection data based on encoding the user data differently from the base set according to the coding mechanism; and a storage circuit configured to store the extra protection data corresponding to the base set. The computing system can further include: an storage circuit configured to: provide a received codeword corresponding to a user data and a base protection data, provide an extra protection data corresponding to the received codeword; a control circuit configured to: decode the received codeword according to a coding mechanism, and further decode the received codeword to recover the user data based on decoding differently from decoding the base set and using the extra protection data according to the coding mechanism.