Abstract: A method and apparatus for configuring or fabricating a small form-factor (“SFP”) non-volatile memory (“NVM”) solid state drive (“SSD”) plug is disclosed. The SFP NVM SSD (“SNS”) plug capable of storing data persistently, in one embodiment, is configured to couple to an SFP socket of a digital processing system capable of accessing external storage. The SFP socket is capable of providing memory access and optical communication. The SNS plug includes a connector, interface module, memory controller, buffer, and NVM chip wherein the digital processing system host performs storage access to the NVM chip via the memory controller.

Abstract: A system configuration containing a host, solid state drive (“SSD”), and controller able to perform a hybrid mode non-volatile memory (“NVM”) access is disclosed. Upon receiving a command with a logical block address (“LBA”) for accessing information stored in NVM, a secondary flash translation layer (“FTL”) index table is loaded to a first cache and entries in a third cache is searched to determine validity associated with stored FTL table. When the entries in the third cache are invalid, the FTL index table in the second cache is searched to identify valid FTL table entries. If the second cache contains invalid FTL index table, a new FTL index table is loaded from NVM to the second cache. The process subsequently loads at least a portion of FTL table indexed by the FTL index table in the third cache.

Abstract: One embodiment of the present invention discloses a shared non-volatile memory (“NVM”) system using a distributed flash translation layer (“FTL”) scheme capable of facilitating data storage between multiple hosts and NVM devices. A process of shared NVM system includes an NVM management module or memory controller able to receive a request from a host for reserving a write ownership. The write ownership allows a host to write information to a portion of storage space in an NVM device. Upon identifying availability of the write ownership associated with the NVM device in accordance with a set of predefined policy stored in the NVM management module, the request is granted to the host if the write ownership is available. The host is subsequently allowed to fetch the FTL snapshot from the NVM device for the write operation.

Abstract: A solid-state drive (“SSD”), in one embodiment, uses a flash translation layer (“FTL”) to implement a wear leveling scheme for improving reliability of non-volatile memory (“NVM”). The SSD, which is a digital processing system operable to store information, includes a digital processing element and NVM device(s). The digital processing element which can be a memory controller is able to facilitate processing and storing data in the NVM device. The NVM device, in one embodiment, is divided the storage space into multiple blocks and each block is further organized in multiple minimum writeable units (“MWUs”) with a mapping table. While MWUs can be pages, the mapping table or address mapping table facilitates address association or map between MWUs and logic block addresses (“LBAs”) in accordance with a predefined wear leveling scheme.

Abstract: One embodiment of the present application discloses a memory system using programmable sequencers to manage and/or communicate with non-volatile memory (“NVM”) devices with different specifications. The memory system capable of storing information includes a scheduler, NVM device, and programmable NVM interface (“PNI”). In one aspect, the PNI is a programmable sequencer or includes a programmable sequencer. The scheduler schedules a sequence of events or commands to implement memory access command(s). For instance, the scheduler can issue a scheduler command associated with a memory access in accordance with one or more instructions initiated from a memory controller. The NVM device stores information persistently. The PNI, in one embodiment, is configured to access information in the NVM device based on programmed operation code (“opcode”) stored in an opcode memory.

Abstract: A method and apparatus configured to restore a flash translation layer (“FTL”) in a non-volatile (“NV”) storage device are disclosed. After reactivating the NV storage device from an unintended system crash, a process of recovering FTL, in one embodiment, receives a request for restoring at least a portion of the FTL or FTL database. After identifying sequence numbers (“SNs”) associated with flash memory blocks (“FMBs”) which are generated during write cycle(s), the SNs are retrieved from the information storage locations such as state information in the FMBs. A portion of the FTL database is subsequently reconstructed in a random access memory (“RAM”) according to the SNs. In an alternative embodiment, logical block addresses (“LBAs”), LBA lists, and/or index tables can also be used to restore the FTL database or table.

Abstract: A non-volatile (“NV”) memory device is able to enhance data integrity using threshold voltage (“Vt”) recalibration based on a selected scheme. Upon receiving a command for reading a data page, the process, in one embodiment, identifies a reference page which is located at a predefined location in a block of the NV memory. After reading the first reference data from the reference page by a reader in response to a first or current Vt, a first bit error rate (“BER”) is generated based on the comparison between the first reference data and the predefined known data pattern. If the first BER is greater than a predefined BER target, a second Vt is subsequently calculated in accordance with the first Vt. When the second BER is equal to or less than the predefined BER target, an optimal Vt is set to the second Vt. There are also two other methods using DC balance coding scheme and counting the number of 1's in the selected data page can be used in recalibrating the threshold voltage.

Abstract: A method and apparatus configured to restore a flash translation layer (“FTL”) in a non-volatile (“NV”) storage device are disclosed. After reactivating the NV storage device from an unintended system crash, a process of recovering FTL, in one embodiment, receives a request for restoring at least a portion of the FTL or FTL database. After identifying sequence numbers (“SNs”) associated with flash memory blocks (“FMBs”) which are generated during write cycle(s), the SNs are retrieved from the information storage locations such as state information in the FMBs. A portion of the FTL database is subsequently reconstructed in a random access memory (“RAM”) according to the SNs. In an alternative embodiment, logical block addresses (“LBAs”), LBA lists, and/or index tables can also be used to restore the FTL database or table.

Abstract: A non-volatile (“NV”) memory device is able to enhance data integrity using threshold voltage (“Vt”) recalibration based on a selected scheme. Upon receiving a command for reading a data page, the process, in one embodiment, identifies a reference page which is located at a predefined location in a block of the NV memory. After reading the first reference data from the reference page by a reader in response to a first or current Vt, a first bit error rate (“BER”) is generated based on the comparison between the first reference data and the predefined known data pattern. If the first BER is greater than a predefined BER target, a second Vt is subsequently calculated in accordance with the first Vt. When the second BER is equal to or less than the predefined BER target, an optimal Vt is set to the second Vt. There are also two other methods using DC balance coding scheme and counting the number of 1's in the selected data page can be used in recalibrating the threshold voltage.

Abstract: A storage device for improving data integrity using a double link RAID scheme is disclosed. The storage device, in one aspect, includes multiple storage blocks, a group of next pointers, and a group of previous pointers. The storage blocks are organized in a sequential order wherein each block is situated between a previous block and a next block. The storage block is a non-volatile memory capable of storing information persistently. Each of the next pointers is assigned to one block to point to the next block. Each of the previous pointers is assigned to one block to indicate the previous block. In one embodiment, a faulty block can be identified in response to a set of next pointers and previous pointers.

Abstract: A method and system for providing a dual memory access to a non-volatile memory device using expended memory addresses are disclosed. The digital processing system such as a computer includes a non-volatile memory device, a peripheral bus, and a digital processing unit. The non-volatile memory device such as a solid state drive can store data persistently. The peripheral bus, which can be a peripheral component interconnect express (“PCIe”) bus, is used to support memory access to the non-volatile memory device. The digital processing unit such as a central processing unit (“CPU”) is capable of accessing storage space in the non-volatile memory device in accordance with an extended memory address and offset.

Abstract: An improved garbage collection (“GC”) process configured to recover new blocks from used storage space is disclosed. After initiating the GC process for a flash memory in accordance with at least one of predefined triggering events, a first valid page within a first block marked as an erasable block is identified. Upon determining a first signature representing the content of the first valid page according to a predefined signature generator, the process identifies a second valid page within a second block as a duplicated page of the first valid page in response to the first signature. The process subsequently associates the logical block address (“LBA”) of the first valid page to the second valid page. In an alternative embodiment, page compression and sequential order of page arrangement can also be implemented to further enhance efficiency of garbage collection.