Abstract: A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.

Abstract: An integrated semiconductor structure comprises two homologous P-type regions formed within an N-type epitaxial layer. A P-type region formed in the portion of the epitaxial layer disposed between the two P-type regions includes within it an N-type region. This N region is electrically connected to the P region by means of a surface metal contact. The structure reduces the injection of current between the first and second P regions, at the same time preventing any vertical parasitic transistors from being switched on.

Abstract: A monolithic, integrated semiconductor circuit comprising a high-voltage ice (210) with a predetermined reverse-conduction threshold comprising a chain of zener diodes (220-240). Device 210 is connected in series with a thermal compensation device (250) constituted by a plurality of Vbe multipliers connected in series with one another. Each of the Vbe multipliers is formed by a resistive divider (R1i, R2i) and a low-voltage transistor (Ti) or two or more low-voltage transistors in a Darlington configuration.

Abstract: Inductive structures make highly efficient use of the magnetic flux generd, and are consistent with integrated circuit manufacturing techniques. The structures include electrically conductive layers and interconnecting conductor filled vias to define a helical winding surrounding a closed magnetic core. The magnetic core may also be formed by semiconductor manufacturing techinuqes. A method of making the structures on a semiconductor substrate concurrently with the formation of the integrated circuit itself is also disclosed.

Abstract: A power semiconductor structure (200), in particular in VIPower technology, made from a chip of N-type semiconductor material (110), comprising a bipolar or field-effect vertical power transistor (125, 120, 110) having a collector or drain region in such N-type material (110); the semiconductor structure comprises a PNP bipolar lateral power transistor (210, 110, 220) having a base region in such N-type material (110) substantially in common with the collector or drain region of the vertical power transistor.

Abstract: A voltage level shift circuit has a first input receiving a first voltage signal and a second input receiving a second voltage signal. The voltage level shift circuit is structured to generate an output voltage at an output terminal which is equal to a sum of the first and second voltage signals. The first voltage signal may be varied to vary a shift of the second voltage signal.

Abstract: The system includes various circuit units each having a capacitor and a charging circuit for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop which uses one of the circuit units as an adjustable oscillator, and current transducer means which regulates the charging currents of the capacitors of the circuit units in dependence on the regulated charging current of the capacitor of the oscillator, or the error current of the PLL loop.

Abstract: A circuit for limitation of maximum current delivered by a power transistor comprises: a network for detection of the current delivered by the power transistor which generates a first electrical signal; a reference network for generating a reference current proportional to a resistor and self-limited, provided by means of a current generator circuit and a limiting circuit with current mirror; and an operational amplifier which compares the first electrical signal with the reference current and which tends to inhibit the power transistor if the current delivered exceeds a certain threshold value.

Abstract: A protection circuit for at least one power transistor which has at least one control terminal and two main conduction terminals defining a main conduction path includes a first detection means designed to generate a first electrical signal approximately proportional to current flowing in the main conduction path. Second detection means are designed to generate a second electrical signal approximately proportional to voltage across the main conduction path. Multiplying means receive at input the first and second signals and are designed to generate an electrical product signal substantially corresponding to the product of at least the latter. A generator generates an electrical reference signal, and operational amplifier means receive at input the product signal and the reference signal and are designed to generate an electrical difference signal substantially corresponding to their difference.

Abstract: The present invention relates to an electronic device integrated monolithlly on a semiconductor material comprising a substrate having a first conductivity type in which are formed first and second diffusion regions of a second conductivity type. The substrate and the first and second diffusion regions defining a base region, a collector region and an emitter region of a parasitic transistor. The second diffusion region includes a third diffusion region having conductivity of the first type to provide in the second diffusion region a resistive path placed in series with the emitter region of the parasitic transistor while backfeeding it negatively and taking it to saturation with a resulting reduction of its current gain and limitation of the maximum current due thereto.

Abstract: A circuit for protecting from overload currents includes an electronic power device having at least first and second terminals and at least one control terminal. The circuit also includes at least one voltage-generating circuit for generating a reference voltage having a predetermined pattern. The voltage-generating circuit includes at least a first terminal connected to the first terminal of the power device and at least a second terminal coupled to the second terminal of the power device through a sensor. The circuit also preferably includes at least one comparator for comparing the reference voltage with a voltage present across the sensor. The comparator has at least one output terminal and at least first and second input terminals. The first and second input terminals are respectively connected to a third terminal of the voltage-generating circuit and the second terminal of the power device.

Abstract: A pulse generator has an input and two outputs at which to respectively generate pulses in relation to different types of signal edges received at the input of the generator. The generator provides two distinct logic circuit blocks of the sequential type, the blocks being mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks, it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract: An oscillating circuit including a capacitor, a charge circuitry and a control circuitry. The charge circuitry includes first and second current generators having respectively first and second current values that are opposite in direction and a switching circuit designed to couple alternately the generators to the capacitor. The control circuitry has a voltage input coupled to the capacitor and an output coupled to control inputs of the switching circuit and includes a comparator with hysteresis having a lower threshold and an upper threshold. The difference between the upper threshold and the lower threshold is chosen to be substantially proportional to the ratio of the product to the sum of the two current values such that the oscillation frequency and the duty cycle do not depend on the supply voltage, the temperature and the process.

Abstract: A device integrated on a chip of a semiconductor material is disclosed which comprises an NPN bipolar transistor and an N-channel MOSFET transistor in an emitter switching configuration, both being vertical conduction types. The bipolar transistor has its base and emitter regions buried; the MOSFET transistor is formed with an N region bounded by the base and the emitter regions and isolated by a deep base contact and isolation region. To improve the device performance, especially at large currents, an N+ region is provided which extends from the front of the chip inwards of the isolated region and around the MOSFET transistor. In one embodiment of the invention, a MOSFET drive transistor is integrated which has its drain terminal in common with the collector of the bipolar transistor, its source terminal connected to the base of the bipolar transistor, and its gate electrode connected to the gate electrode of the MOSFET transistor in the emitter switching configuration.

Abstract: A high-voltage resistor integrated on a semiconductor substrate with opposite sign conductivity, and being of a type with one end connected to the substrate and another end connected to a lower electric potential than the substrate, further comprises at least one thin layer of the field plate type covering at least a section of the resistor.

Abstract: A spiral resistor being of a type formed on a semiconductor substrate to withstand high voltages, comprises at least one thin field-plate layer covering said substrate between adjacent turns of the resistor. This prevents the well-known phenomenon of the "phantom gate" from occurring which would result in the characteristics of spiral resistors deteriorating over time.

Abstract: A charge pump circuit includes a pair of series switching devices coupled between an output node of the circuit and an input node. A power stage drives a charge transfer capacitor which is coupled to an intermediate node between the series switching devices. The power stage has an input coupled to the input node of the circuit, The power stage further includes a bootstrap capacitor for maintaining a conductive state during an entire half of a cycle of a period of oscillation of a local oscillator. The series switching devices may be driven in phase opposition by either a CMOS invertor or a pair of comparators.