Abstract: An ultrasound automated detection and display method of cranial abnormal regions includes: firstly, a skull surface model is constructed; then contour detection is carried out based on a two-dimensional ultrasonic image to obtain a skull contour curve; fitting is carried out on the contour curve and the skull surface model to determine whether the two-dimensional ultrasonic image has symmetry characteristics or not; finally, similarity comparison calculation is carried out on two mutually symmetrical regions by utilizing the symmetry characteristics of the two-dimensional image, so that whether an abnormal region exists and the location of the abnormal region is determined. The method has the advantages that a skull surface model is constructed before detecting a cranial contour curve on a two-dimensional ultrasonic image.

Abstract: An antenna device includes a casing, a circuit board, and an antenna. The casing has a positioning structure. The circuit board is disposed in the casing. The antenna is disposed in the casing and includes a main body portion and a connection portion connected to each other. The connection portion is connected to a surface of the circuit board. The main body portion is extended on a plane defined by a first axial direction and a second axial direction. The first axial direction is perpendicular to the surface and the second axial direction is parallel to the surface. The main body portion is positioned on the positioning structure and separated from the circuit board.

Abstract: A memory device includes a memory cell array, a reference generating circuit, a row decoding circuit that is connected to the memory cell array through word lines, a page buffer circuit that is connected to the memory cell array through bit lines, a data input/output circuit that is connected to the page buffer circuit through a data line, a buffer circuit, a control logic circuit that performs logic sequences, based on the internal clock signal and the internal power, and a test mode circuit. When the memory device enters a test mode, the test mode circuit disables a part of components of the reference generating circuit. In the test mode, the control logic circuit performs the logic sequences by using an external clock signal provided from an external device.

Abstract: A wiring substrate includes a first wiring part including a first insulating layer and a first conductor layer laminated on the first insulating layer, and a second wiring part including a second insulating layer and a second conductor layer laminated on the second insulating layer. The thickness of the second insulating layer is smaller than that of the first insulating layer. The thickness of the second conductor layer is smaller than that of the first conductor layer. The first conductor layer includes first wirings including differential wirings having the minimum wiring width of larger than 5 ?m and minimum inter-wiring distance of larger than 7 ?m. The second conductor layer includes second wirings having the maximum wiring width of 5 ?m or less and the maximum inter-wiring distance of 7 ?m or less. The second part is positioned closer to the outermost surface of the substrate than the first part.

Abstract: A semiconductor device includes a substrate including a cell array region and a core region disposed around the cell array region; a plurality of storage element contacts; a contact plug; and a contact plug spacer. The plurality of storage element contacts may include a first storage element contact and at least one second storage element contact, the first storage element contact is a closest storage element contact of the plurality of storage element contacts to the core region, such that the first storage element contact is between the core region and the at least one second storage element contact. A step difference in a vertical direction perpendicular to the substrate between a top surface of the first storage element contact and a top surface of the at least one second storage element contact is 5 nm or less.

Abstract: A compound having a (poly)glycerin skeleton with an average degree of polymerization of 1-100, and which contains a (poly)glycerin-based alkoxysilane having an alkoxysilyl group.

Abstract: The present invention relates to the technical field of molecular biology, and in particular, to a mutant-type RNase R and a preparation method therefor and application thereof. The mutant-type RNase R provided by the present invention is designated RNase R__?M8, an amino acid sequence of which is shown as SEQ ID NO. 5, and a nucleotide sequence encoding the amino acid sequence is shown as SEQ ID NO. 6. Preparation processes of the mutant-type RNase R_?M8 provided by the present invention include vector construction, vector transformation, protein induction expression, bacteria collection, protein purification, activity assay, etc. The mutant-type RNase R provided by the present invention improves the expression yield and salt tolerance of RNase R and is beneficial to meeting diverse RNA sample requirements.

Abstract: A test method, a test apparatus, a test system, and a storage medium are provided, so as to solve the technical problem of how the leakage of a battery cell is detected. The test method of this embodiment of this application includes: (S10) obtaining a CAN signal output by a gas sensor, where the gas sensor is disposed on a test box, and a battery cell is placed in the test box; (S20) determining a gas concentration of a predetermined gas in the test box based on the CAN signal; and (S30) sending a concentration exceedance signal when the gas concentration is higher than a concentration threshold.

Abstract: A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.

Abstract: Provided are a method and apparatus for identifying a malicious mining behavior, an electronic device, and a storage medium. The method includes: obtaining operation data corresponding to a target operation, on capturing of the target operation; extracting a wallet address from the operation data to obtain a wallet address set obtaining data of a network outgoing connection for external access, and determining whether the data of the network outgoing connection comprises a wallet address belonging to the wallet address set and determining that the data of the network outgoing connection corresponds to the malicious mining behavior, on determining that the data of the network outgoing connection comprises a wallet address belonging to the wallet address set.

Abstract: Disclosed are an artificial implant and a method for manufacturing same, the artificial implant comprising: a silicone shell consisting of an upper portion, a lower portion, and a side portion; and a filler injected into the silicone shell, wherein the silicone shell includes at least one silicone layer and at least one reinforcing layer, the reinforcing layer being provided on at least a portion of the lower portion and the side portion of the silicone shell, or the silicone shell includes a layered structure having a step.

Abstract: The present invention relates to an ice maker. Specifically, according to one embodiment of the present invention, an ice maker may be provided, comprising: a refrigerant pipe having formed therein a pipe flow path for a refrigerant to flow through; a finger protruding from the refrigerant pipe and having formed therein a finger space that communicates with the pipe flow path for the refrigerant to flow through; a heater comprising a heating part provided in the refrigerant pipe to heat the finger, and an extension part extending from one end of the heating part to the outside of the refrigerant pipe; a heater holder that surrounds at least a portion of the extension part; and a sealing element for preventing the introduction of moisture through a gap between the outer peripheral surface of the extension part and the inner peripheral surface of the heater holder.

Abstract: Provided is an apparatus for processing a substrate, the apparatus including: a liquid treatment chamber; a drying chamber; and a light treatment chamber, in which the light treatment chamber includes: a treatment housing having a treatment space in which the substrate is processed; a support member for supporting the substrate in the treatment space; a light source for irradiating the substrate supported on the support member with light in the form of pulses; and a light filter for selecting a set range of wavelengths of the light generated by the light source and allowing the selected wavelengths to pass through.

Abstract: An integrated circuit (IC) device includes a substrate, a pair of fin-type active regions protruding from the substrate to define a trench region on the substrate, the fin-type active regions extending in a first lateral direction, a pair of source/drain regions on the fin-type active regions, respectively, a device isolation film in the trench region, the device isolation film apart from the substrate in a vertical direction, an etch stop structure filling at least a portion of the trench region between the substrate and the device isolation film, a via power rail between the pair of fin-type active regions and between the pair of source/drain regions, the via power rail passing through at least a portion of the etch stop structure, and a backside power rail passing through the substrate, the backside power rail in contact with one end of the via power rail.

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

Abstract: A Surface Acoustic Wave (SAW) Impedance Element Filter (IEF) comprises a cascade of Gamma sections. Each of the Gamma sections comprises a series SAW resonator and a shunt SAW resonator deposited in a surface of a piezoelectric substrate with an additional capacity connected in parallel to the shunt SAW resonator. All the series and shunt SAW resonators have pitches (P) which are substantially equivalent. The SAW IEF has smaller bandwidth to satisfy some specific applications.

Abstract: A noise reduction circuit includes a surface-mount common mode choke coil mounted on a circuit board. Output terminals of the common mode choke coil are connected to an input capacitor via second circuit patterns. Two terminals of the input capacitor are connected to two input ends of a switching circuit via third circuit patterns. Path lengths of the second circuit patterns are longer than path lengths of the third circuit patterns. Of a plurality of current paths, the path lengths of the third circuit patterns are shortest in comparison with path lengths of other current paths. First circuit patterns are parallel and face each other to form a first parasitic capacitance, and the second circuit patterns are parallel and face each other to form second parasitic capacitances.

Abstract: The embodiments of the present disclosure provide a method and an Internet of Things system for determining and allocating gas maintenance tasks based on smart gas. The method includes: obtaining maintenance personnel information of at least one maintenance personnel; obtaining second positioning information corresponding to at least one maintenance task; determining at least one candidate maintenance task based on the first positioning information and the second positioning information; determining a maintenance cost score of each of the at least one maintenance personnel through a cost prediction model based on task data of the at least one candidate maintenance task and the historical maintenance data of the maintenance personnel; determining a candidate maintenance personnel corresponding to the at least one candidate maintenance task based on the maintenance cost score; and sending the at least one candidate maintenance task to a user terminal of the candidate maintenance personnel.

Abstract: An action control device includes a sound acquirer, an actuator, and a controller. In response to the controller determining, during an action of the actuator, that a sound acquired by the sound acquirer is a human voice, the controller controls so as to stop the actuator, capture sound after the determination for a predetermined period, and in response to the predetermined period having elapsed, restart the action of the actuator.

Abstract: A display apparatus is provided. The display apparatus includes a display and a processor configured to count time for operating a screen saver after a user input is received, and based on the counted time corresponding to a threshold time, control the display to display a screen corresponding to the screen saver by operating the screen saver.