Abstract: An on-device training-based user recognition method includes performing on-device training on a feature extractor based on reference data corresponding to generalized users and user data, determining a registration feature vector based on an output from the feature extractor in response to the input of the user data, determining a test feature vector based on an output from the feature extractor in response to an input of test data, and performing user recognition on a test user based on a result of comparing the registration feature vector to the test feature vector.

Abstract: A resin composition for a sealant has excellent heat-sealing strength with respect to a substrate, and a reduced elution amount thereof into normal heptane. A resin composition for a sealant includes: a resin (A) which is an ethylene-(meth)acrylic acid ester copolymer in which a content of a (meth)acrylic acid ester unit is from 10% by mass to 25% by mass; and a tackifying resin (B), in which a content of the resin (A) is more than 45% by mass with respect to a total amount of resin components in the resin composition for a sealant, and a content of the tackifying resin (B) is from 0.1% by mass to 10% by mass with respect to the total amount of the resin components in the resin composition for a sealant.

Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: A random access method, a random access apparatus, an electronic device and a computer-readable storage medium are disclosed. The method includes: initiating random access by transmitting a preamble and an identity to a base station; receiving a message fed back by the base station for the preamble and the identity, in which the message includes at least one information unit, and different information units are configured to indicate different results of initiating random access through the user equipment; and performing an operation corresponding to a result of initiating random access indicated by the information unit in the message.

Abstract: This application provides a vehicle and a control method for a vehicle suspension. The vehicle includes a first component, a second component, and a vehicle suspension. The vehicle suspension is located between the first component and the second component. The first component is a component that the vehicle suspension bears, the second component is configured to bear the vehicle suspension and the first component, and the vehicle suspension includes a variable damper connected between the first component and the second component. The variable damper is configured to provide a first force to the first component based on a first acceleration of the first component, to control a displacement of the first component relative to the second component in a height direction of the vehicle. In the embodiments of this application, bumps in a driving process of the vehicle can be effectively reduced, so that vehicle ride comfort is improved.

Abstract: A battery pack includes a battery cell, an input/output terminal to/from which a charging/discharging current of the battery cell is to be inputted/outputted, and a connector detachably connected to the input/output terminal, and the input/output terminal includes a first hollow conductive member protruding in a first direction and a second hollow conductive member protruding to surround an outer periphery of the first hollow conductive member, the connector includes a central guide protruding in a second direction opposite to the first direction and a third hollow conductive member protruding to surround the outer periphery of the central guide, the central guide is fitted into a hollow portion of the first hollow conductive member, and the third hollow conductive member is fitted into a space between the first and second hollow conductive members and is electrically connected to the first and second hollow conductive members by an elastic connection member.

Abstract: The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.

Abstract: A circuit board according to an embodiment includes: a substrate including one surface and the other surface; a first circuit pattern disposed on the one surface; and a second circuit pattern disposed on the other surface, wherein at least one via is formed in the substrate, and the first circuit pattern and the second circuit pattern are wire-bonded through the via to conduct electricity.

Abstract: Disclosed is a method for producing a spherical neural mass having suppressed teratoma formation. When using the spherical neural mass produced according to the method of the present disclosure, the purity of the neuronal progenitor cells may be improved, the teratoma formation may be suppressed, and the viability and recovery percentage of the cell may be increased.

Abstract: The present disclosure provides a solar reflecting film and a preparation method thereof. The solar reflecting film includes a substrate and a functional layer stacked on each other. The functional layer includes a first reflecting layer, a barrier layer, and a second reflecting layer stacked on the substrate in order. The barrier layer includes a first barrier layer and a second barrier layer stacked on the first barrier layer. The first barrier layer is metal fluoride, inorganic non-metallic oxide, metal oxide or a combination thereof. The second barrier layer is metal oxides, metal nitrides, semiconductor doped compounds or a combination thereof. And a material of the first barrier layer is at least partially different from that of the second barrier layer.

Abstract: A housing of a centrifugal fan, a centrifugal fan and a clothes dryer; a layered structure is provided within an air duct of the housing, and the layered structure is configured to be able to divide at least a part of the air duct into at least two air layers, the width of an air layer close to a strong air end being greater than the width of an air layer close to a weak air end. Also disclosed are a centrifugal fan having the housing and a clothes dryer having the centrifugal fan. By the layered structure being disposed within the air duct, the air duct is divided into at least two air layers, and the width of the wind layer close to the strong wind end is greater than the width of the wind layer close to the weak wind end.

Abstract: A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region.

Abstract: Disclosed are a voltage compensation method and device of a voltage reducing circuit. The voltage compensation method includes: determining a capacitance value of each capacitor and a resistance value of each resistor in a voltage compensation circuit according to a voltage compensation expectation of the voltage reducing circuit; determining each zero and each pole of a transfer function of the voltage compensation circuit according to the capacitance value of each capacitor and the resistance value of each resistor; setting each capacitor and the resistor not in direct connection with the capacitor in series to have a positive temperature coefficient, and setting the resistor in direct connection with the capacitor in series to have a negative temperature coefficient; and compensating voltage for the voltage reducing circuit by using the voltage compensation circuit to output a rated voltage.

Abstract: An electronic device is provided.

Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.

Abstract: The present invention discloses a chemical mechanical polishing slurry, and the chemical mechanical polishing slurry comprises silica abrasive particles and accelerating agents, wherein the accelerating agents are selected from pyridine compound, piperidine compound, pyrrolidine compound or pyrrole compound and their derivatives, which have one or more carboxyl groups, and pyrimidine compound and its derivatives, which have one or more amino groups. The chemical mechanical polishing slurry can simultaneously increase the removal rate of both silicon nitride and polysilicon.

Abstract: A communication system includes a first communication device that configures a first wireless network together with another peripheral device or a plurality of other peripheral devices by using a first BSSID and a second communication device that configures a second wireless network together with another peripheral device or a plurality of other peripheral devices by using a second BSSID. The first communication device is configured to transmit a first frame in which a first identification value has been designated as a BSSID. The first communication device and the second communication device are configured to perform reception processing of a frame in which the first identification value has been designated as the BSSID, as a valid frame.

Abstract: The invention relates to a driver (100) for emergency lighting means (101), comprising output terminals (111a-b) for electrically supplying at least one emergency lighting means (101), and a test switch (103) for starting a test routine controlled by a controller (109) of the driver (100), wherein the driver (100) is settable to a commissioning mode if the test switch (103) is activated according to a predefined operation pattern defined by time durations and/or repetition criteria of the operation pattern.