Abstract: Provided is an analog switch circuit including an intermediate node, a first PMOS transistor including a source connected to the input node and a back gate and a drain connected to the intermediate node, a second PMOS transistor including a source connected to the output node, a back gate and a drain connected to the intermediate node, and a gate connected to a gate of the first PMOS transistor, a first NMOS transistor including a source grounded and a drain connected to the gates of the first PMOS transistor and the second PMOS transistor, a third PMOS transistor connected between the intermediate node and the drain of the first NMOS transistor, a first resistor connected between the gate of the first NMOS transistor and a ground, and a driver including an input that receives the control signal and an output connected to the gate of the first NMOS transistor.
Abstract: The present disclosure is directed to methods and systems for analyzing integrated circuits. The method includes performing a first resistor capacitor (RC) extraction process on a power-receiving circuit and producing a first RC model. The method also includes scanning a netlist of a power distribution network, the power distribution network electrically connected to the power-receiving circuit. The method further includes determining a selection of circuit elements of the power distribution network based on a predetermined criteria. The method further includes performing a second RC extraction process on the selection of circuit elements and producing a second RC model. The method further includes performing a simulation process on the power-receiving circuit and the power distribution network using the first and second RC models.
Abstract: A display device includes a display panel and an input sensing layer. The display panel includes a base layer including a first island part, a second island part, and a connection part. Sensing patterns of the input sensing layer include a first sensing line pattern disposed on both the first island part and the second island part, and a second sensing line pattern disposed on the connection part. The connection part is an area to which stress is applied as the display device is modified in shape. The second sensing line pattern is disposed on an area of the connection part to which relatively less stress is applied.
Type:
Grant
Filed:
September 28, 2023
Date of Patent:
June 3, 2025
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Byeong-Hee Won, Jun Hyeong Park, Ho-Sik Shin, Jaemin Shin, Hyejin Joo
Abstract: An optical imaging lens, in order from an object side to an image side along an optical axis, includes a first optical assembly, a second optical assembly, a third optical assembly, an aperture, a fourth optical assembly, a fifth optical assembly, and a sixth optical assembly, wherein two of the first optical assembly, the second optical assembly, the third optical assembly, the fourth optical assembly, the fifth optical assembly, and the sixth optical assembly are a compound lens formed by adhering at least two lenses, while the others are single lens, thereby achieving the effect of high image quality and low distortion and satisfying the imaging requirement of visible light during the day and infrared light at night.
Abstract: A method for providing a messenger service, which is performed by at least one processor, includes: creating a conversation group by grouping conversations relevant to a first conversation of a plurality of conversations displayed in a chat room; and providing at least one recommended target screen based on a target-relevant word included in the conversation group.
Abstract: A display panel includes pixels overlapping a scan driving circuit and pixels spaced apart from the scan driving circuit. The display panel further includes a conductive pattern including a plurality of through holes, and the through holes are spaced apart in a plan view from a first electrodes of the pixels overlapping the scan driving circuit.
Abstract: Provided are compounds represented by Formula IA: (IA), and the pharmaceutically acceptable salts and solvates thereof, wherein R, R1a, R1b, L1, L2, L3, X, A, B and C are as defined as set forth in the specification. Also provided compounds of Formula IA for use to treat a condition or disorder responsive to Mcl-1 inhibition such as cancer.
Type:
Grant
Filed:
January 22, 2020
Date of Patent:
June 3, 2025
Assignees:
ASCENTAGE PHARMA (SUZHOU) CO., LTD., REGENTS OF THE UNIVERSITY OF MICHIGAN, ASCENTAGE PHARMA GROUP CORP LIMITED
Abstract: A liquid-containing combination container includes a first container that contains a liquid, a second container that contains the first container and that has an oxygen barrier property, and an oxygen absorber that absorbs oxygen in the second container. The first container includes a container body that includes an opening portion and a stopper that closes the opening portion, the stopper has oxygen permeability.
Abstract: A display device includes a structured light-emitting end, a structured light-receiving end, and a display panel. The structured light-emitting end and the structured light-receiving end are disposed on the backlight surface of the display panel. The structured light-receiving end is disposed opposite to the first display area, and the structured light-emitting end is disposed opposite to the second display area. The first display area of the display device is provided with multiple first pixel driving circuits and multiple first light-emitting units. The vertical projection of each first pixel driving circuit on the backlight surface of the display panel overlaps the vertical projection of one first light-emitting unit, which is connected to the each first pixel driving circuit, on the backlight surface of the display panel.
Abstract: A mixing device includes a mixing container for receiving mixing material and a mixer cover, wherein a first seal and a second seal is provided between the mixing container and the mixer cover. The first seal and the second seal are so arranged that a first air space is formed between the first seal and the second seal.
Type:
Grant
Filed:
March 14, 2019
Date of Patent:
June 3, 2025
Assignee:
Maschinenfabrik Gustav Eirich GmbH & Co. KG
Inventors:
Andreas Seiler, Stefan Münkel, Tobias Matter
Abstract: A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.
Type:
Grant
Filed:
January 5, 2022
Date of Patent:
June 3, 2025
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Chungman Kim, Bonwon Koo, Dongho Ahn, Kiyeon Yang, Zhe Wu, Chang Seung Lee
Abstract: A display substrate includes a base substrate and a plurality of sub-pixels. A sub-pixel includes a pixel electrode and an effective light-emitting region. The pixel electrode includes a main body portion and a connection portion that are interconnected. Shapes of the main body portion and the effective light-emitting region are the same, and at least partial borders of the main body portion and the pixel electrode coincide. The plurality of sub-pixels at least includes a first sub-pixel and a second sub-pixel, and light emitted by the first sub-pixel and second sub-pixel is the same.
Abstract: A display panel in one example includes a substrate, an anode including an emission region on the substrate, a reference voltage line adjacent to the anode, and a branch line connected to the reference voltage line to apply a reference voltage from the reference voltage line to the anode via a switching element. The branch line includes a semiconductor layer, and the branch line is between the reference voltage line and the anode.
Type:
Grant
Filed:
January 29, 2024
Date of Patent:
June 3, 2025
Assignee:
LG DISPLAY CO., LTD.
Inventors:
Dong Yoon Lee, Kwang Yong Choi, Seong Hwan Hwang, Byeong Uk Gang, Hye Min Park
Abstract: A pixel arrangement structure of an OLED display is provided. The pixel arrangement structure includes: a first pixel having a center coinciding with a center of a virtual square; a second pixel separated from the first pixel and having a center at a first vertex of the virtual square; and a third pixel separated from the first pixel and the second pixel, and having a center at a second vertex neighboring the first vertex of the virtual square.
Abstract: A secondary battery configured so as to comprise: a plurality of positive electrodes each including a positive electrode core and a positive electrode active substance disposed on the positive electrode core; a plurality of negative electrodes each including a negative electrode core and a negative electrode active substance disposed upon the negative electrode core; at least one separator; and an adhesive coated so as to have a substantially constant area density on at least one side surface in the thickness direction of the separator. The secondary battery includes a laminated section in which the positive electrodes and the negative electrodes are alternately stacked, having the separator therebetween. The area of adhered sections adhered by the adhesive is greater on the outside in the lamination direction of the laminated section than on the inside in the lamination direction.
Abstract: The present invention discloses an ultra-thin super junction IGBT and a manufacturing method thereof, comprising: a metalized collector; a P-type collector region located on the metalized collector; an N-type FS layer located above the P-type collector region; an N-type FS isolating layer located above the N-type FS layer; a first N-type epitaxial layer located above the N-type FS isolating layer and a second N-type epitaxial layer located above the first N-type epitaxial layer; and a MOS structure located in the second N-type epitaxial layer. According to the present invention, thinning the chip thickness reduces forward conduction voltage drop and switching losses, while reducing thermal resistance and improving current conducting capability.