Abstract: A FIFO uses a fill indicator circuit to indicate a fill status and provide control signals to a data source and data sink to cease operation. A serial string of FIFO cells propagates data from input to output by sending request and acknowledge signals between adjacent cells. The request signal initiates data transfer to the next logical cell and the acknowledge signal indicates completion of the transfer. The fill indicator has one cell for each FIFO cell for monitoring the request and acknowledge signals looking for predetermined state sequences to indicate whether each FIFO cell is full or empty.

Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer and refresh data through the flipflop.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. A programmable divider latches a program integer for providing a latch integer, compares the latch integer to a constant integer, and generates a flag signal having a first state when the latch integer mismatches the constant integer and a second state when the latch integer matches the constant integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for providing the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal.

Abstract: A voltage controlled oscillator runs at full speed to generate an output frequency dependent on temperature and process variation. First and second clock signals are generated from the oscillator signal, while third and fourth clock signals are developed in response to an input clock signal. The number of clock signals occurring during a first state of the third clock signal are counted for providing a plurality of output signals also indicative of the temperature and process variation. The plurality of output signals compensate an input signal for the temperature and process variation for providing an output signal.

Abstract: A charge pump in a phase lock loop equalizes the charge and discharge currents flowing into the filter capacitor independent of the loop node voltage for providing a linear VCO output frequency. The potential at the output of the charge pump determines whether the charging/discharging current is decreased or increased. An active up control signal to increase VCO output frequency and a low level potential at the output of the charge pump limits the charging current to the loop filter while increasing the discharge current. An active down control signal to decrease the VCO output frequency and a high potential at the output of the charge pump limits the discharging current while increasing the charge current. The voltage change at the output of the charge pump in response to the up control signal is made equal to the voltage change during the down control signal for providing equal charge and discharge currents to the loop filter independent of the loop voltage.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal when the first and second digital input signals have a first logic state at a first transition of a control signal and a second logic state at a second transition of the control signal. One false lock triggers an out-of-phase status indicator. The lock detection signal must return to a valid state for a predetermined number of periods before the phase lock status indicates a valid lock condition. The first and second digital input signals may operate with a non-50% duty cycle.

Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A voltage controlled oscillator (VCO) includes a voltage controlled load. The voltage controlled load supplies additional capacitive loading to the VCO, via a transmission gate, at low frequencies to decrease the frequency-gain factor of the VCO. Moreover, at high frequencies, the effect of the voltage controlled load is minimized by turning off the transmission gate thereby allowing the VCO to operate at maximum frequency for worst case speed conditions.

Abstract: A voltage controlled oscillator (VCO) generates a 50% duty cycle clock. The 50% duty cycle clock is derived directly from the operating frequency of the VCO thereby abating the need for the VCO to operate at twice the desired clock frequency. This allows the VCO to be utilized in high frequency phase-locked loop systems.

Abstract: A frequency divider circuit is responsive to first and second digital input signals and an input clock signal for providing an output clock signal operating at a frequency equal to that of the input clock signal divided by the ratio of the first and second digital input signals. A register is initialized to a predetermined digital value for providing a first digital output signal. The first digital input signal is subtracted from the first digital output signal to form a second digital output signal for the first logic state of a digital control signal; otherwise the second digital output signal is set equal to a least significant portion of the first digital input signal for the second logic state of the digital control signal. The second digital output signal and the second digital input signal are added together for providing the next value of the first digital output signal which is stored back in the register to repeat the cycle.

Abstract: An expandable first-in-first-out FIFO circuit is provided for storing data words in a plurality of data cells in response to a digital position control signal generated by a plurality of control cells such that the oldest data word is always present at the output data bus. The data cells are arranged in pairs for data transferring therebetween whereby the data words are placed in the upper and lower data cells of each pair before allocating data cells farther from the input data bus. The digital position control signal is represented as a first portion having a first logic state and a second portion having a second logic state, the boundary of which determines the occupied portion of the data cells which provides control of the movement of data words therein. The FIFO circuit is expandable without modification of the preexisting data cells or control cells simply by adding data cell pairs and associated control cells.