Abstract: A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.

Abstract: An SRAM bit cell with cross-coupled inverters has separate write and read buses. Writing is performed through an NMOS pass transistor. Reading is performed through a PMOS transistor. Because the NMOS transistor does not pass a logic 1 as easily as logic 0, assistance is needed to speed up writing of a logic 1 value relative to the time required to write a logic 0 value. An NMOS pre-charge transistor is coupled between the read bus and ground potential; and, a read is performed simultaneously with a write. This conditions the cell by weakening one of the inverters, such that they cross-couple more quickly when a logic 1 value is written into the cell. Alternatively, a single-ended read/write bus can be coupled to the NMOS pass transistor with write-assistance provided by grounding the PMOS pass transistor.