Patents Assigned to Coherent Logix, Incorporated
  • Patent number: 10893085
    Abstract: A system and method for wirelessly transmitting audiovisual information. A first plurality of packets including audiovisual information may be generated. A second plurality of packets including error correction coding information for the audiovisual information may be generated. Control information for associating the error correction coding information with the audiovisual information may be generated, and a third plurality of packets including the control information may also be generated. The plurality of packets, including the first, second, and third pluralities of packets, may be transmitted to a mobile device in a wireless manner. The control information may inform the mobile device of the association of the first error correction coding information with the audiovisual information.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: January 12, 2021
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 10887879
    Abstract: Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: January 5, 2021
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Feng Liu
  • Patent number: 10873754
    Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 22, 2020
    Assignee: Coherent Logix, Incorporated
    Inventors: Michael W. Bruns, Martin A. Hunt, Manjunath H. Siddaiah, John C. Sievers
  • Patent number: 10848811
    Abstract: Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 24, 2020
    Assignee: Coherent Logix, Incorporated
    Inventors: Colleen J. McGinn, Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 10838787
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 17, 2020
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka
  • Patent number: 10776085
    Abstract: A computer-implemented method for creating a program for a multi-processor system comprising a plurality of interspersed processors and memories. A user may specify or create source code using a programming language. The source code specifies a plurality of tasks and communication of data among the plurality of tasks. However, the source code may not (and preferably is not required to) 1) explicitly specify which physical processor will execute each task and 2) explicitly specify which communication mechanism to use among the plurality of tasks. The method then creates machine language instructions based on the source code, wherein the machine language instructions are designed to execute on the plurality of processors. Creation of the machine language instructions comprises assigning tasks for execution on respective processors and selecting communication mechanisms between the processors based on location of the respective processors and required data communication to satisfy system requirements.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 15, 2020
    Assignee: Coherent Logix, Incorporated
    Inventors: John Mark Beardslee, Michael B. Doerr, Tommy K. Eng
  • Patent number: 10747709
    Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 18, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
  • Patent number: 10747689
    Abstract: Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: August 18, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino
  • Patent number: 10691451
    Abstract: Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 23, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Keith M. Bindloss, Carl S. Dobbs, Evgeny Mezhibovsky, Zahir Raza, Kevin A. Shelby
  • Patent number: 10685143
    Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 16, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Michael B. Doerr, Carl S. Dobbs, Michael B. Solka, Michael R. Trocino, David A. Gibson
  • Patent number: 10666998
    Abstract: Control information for configuring an audiovisual device to present multimedia content according to a first service type may be generated. A method may include generating first control information for configuring an audiovisual device to decode a multimedia stream, generating first data that indicates a structure of the first control information, and transmitting the first data and the first control information. The first control information may be generated according to a first protocol version. Second data and second control information may be similarly generated and transmitted according to a second protocol version. Disclosed techniques may facilitate receiving devices to determine whether they support received wireless transmissions and decode the transmissions based on the control information.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 26, 2020
    Assignee: Coherent Logix, Incorporated
    Inventors: Colleen J. McGinn, Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 10601445
    Abstract: Wireless transport of multiple service versions of a transport framework. First and second information may be processed for transmission, respectively, according to first and second service versions of a transport framework. The first and second information may be encoded using a first type of error correction coding; after processing, the processed first information may include error correction coding according to the first type of error correction coding, while the processed second information may remain uncoded according to the first type of error correction coding. Control information may be generated indicating that the second information remains uncoded according to the first type of error correction coding, which may signal to receivers that the second information is processed according to the second service version of the transport framework.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 24, 2020
    Assignee: Coherent Logix, Incorporated
    Inventors: Kevin A. Shelby, Peter J. Nysen, Michael B. Doerr
  • Patent number: 10594438
    Abstract: Methods and devices are described for determining reliabilities of bit positions in a bit sequence for information bit allocation using polar codes. The reliabilities are calculated using a weighted summation over a binary expansion of each bit position, wherein the summation is weighted by an exponential factor that is selected based at least in part on the coding rate of the polar code. Information bits and frozen bits are allocated to the bit positions based on the determined reliabilities, and data is polar encoded as the information bits. The polar encoded data is then transmitted to a remote device.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 17, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventor: Kevin A. Shelby
  • Patent number: 10592233
    Abstract: Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In some embodiments, software code may include first program instructions executable to perform a function. In some embodiments, the software code may also include one or more language constructs that are configurable to specify one or more parameter inputs. In some embodiments, the one or more parameter inputs are configurable to specify a set of hardware resources usable to execute the software code. In some embodiments, the hardware resources include multiple processors and may include multiple supporting memories.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: March 17, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Stephen E. Lim, Viet N. Ngo, Jeffrey M. Nicholson, John Mark Beardslee, Teng-I Wang, Zhong Qing Shang, Michael Lyle Purnell
  • Patent number: 10567971
    Abstract: A broadcast/broadband convergence system that delivers content from content sources to user equipment devices. The system provides: significantly enhanced mobile capability to the broadcast industry; an additional revenue source for the broadcast industry by dynamically selling available spectral resources for use by wireless broadband networks and/or broadcast content off-loaded from wireless broadband networks; additional spectrum for the broadband industry through the dynamic purchase of available spectrum; and an enriched user experience. A spectrum server may facilitate the dynamic allocation of radio spectrum made available by the broadcast networks. The broadcast networks may broadcast with enhanced waveform parameters to support mobile devices as well as fixed devices.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: February 18, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Tommy K. Eng, Kevin A. Shelby
  • Patent number: 10567981
    Abstract: Techniques for operating a wireless network in a plurality of radio operating environments are disclosed. In some embodiments, an apparatus receives a first parameter value set that is selected from a group of multiple parameter value sets, wherein the first parameter value set is appropriate for a first target radio operating environment that corresponds to one or more of: a first level of mobility of user devices or a first range of wireless transmission. In some embodiments, the apparatus is reconfigured to receive wireless broadcast transmissions from a second broadcast transmitter using a second parameter value set that is appropriate for a second target radio operating environment. The first and second broadcast transmitters may be the same or different. The parameter value sets may include a first parameter based upon which the apparatus is configured to determine subcarrier spacing and a second parameter that indicates a cyclic prefix size.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: February 18, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Tommy K. Eng, Kevin A. Shelby
  • Patent number: 10560299
    Abstract: Techniques are disclosed relating to generating and receiving radio frames with multiple portions that have different encoding schemes. An apparatus may include one or more processing elements configured to receive, via a wireless radio, wireless data that includes a plurality of portions that each include multiple orthogonal frequency-division multiplexing (OFDM) symbols. Different ones of the portions have different frequency transform sizes and different sampling rates. The wireless data may also include control data that indicates the frequency transform sizes and sampling rates for the ones of the portions. The apparatus may select, based on the control data and a determined velocity of the apparatus, one or more but not all of the plurality of portions and may decode the selected one or more portions to determine data represented by the OFDM symbols in the selected one or more portions. Different portions of the wireless data may be adapted for decoding by devices moving at different maximum velocities.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: February 11, 2020
    Assignees: COHERENT LOGIX, INCORPORATED, SINCLAIR TELEVISION GROUP, INC.
    Inventors: Michael J. Simon, Kevin A. Shelby, Mark Earnshaw
  • Patent number: 10560932
    Abstract: Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 11, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Kevin A. Shelby, Feng Liu
  • Patent number: 10536305
    Abstract: Methods and devices are described for polar encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on control information blind detection and decoding. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a user equipment (UE)-specific identifier, a UE group identifier, or a base station identifier. Frozen bits of the polar code may be used to encode and transmit hybrid automatic repeat request (HARQ) acknowledgment messaging for early retransmission of unsuccessful downlink messages. A tiered process of UE identification may be employed to improve a balance between early termination of the decoding process and success of the UE identification process.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 14, 2020
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Kevin A. Shelby, Feng Liu, David R. Starks, Mark Earnshaw
  • Patent number: 10521285
    Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: December 31, 2019
    Assignee: COHERENT LOGIX, INCORPORATED
    Inventors: Carl S. Dobbs, Michael R. Trocino, Michael B. Solka