Abstract: A memory device for a mobile communication device. The device includes a pseudo static random access memory (PSRAM), a NAND flash memory, an interface controller and a NOR flash memory. When the mobile communication device is powered on, the microprocessor downloads a system program to the PSRAM from the NAND flash memory and shows a startup icon on a display unit according to an initial program, executing the downloaded system program in the PSRAM to accomplish startup of the mobile communication device.

Abstract: A memory device with power-saving mode. A memory unit is coupled to an electronic device to access desired data according to an input signal, wherein the electronic device has an operating voltage and the memory unit comprises an input buffer, a decoder, a memory array, an output buffer and a DC voltage generator. A voltage detector is coupled to the electronic device to detect operating voltage. When operating voltage falls below a predetermined value, and outputs a disable signal to turn off the input buffer and the output buffer, or enters a power-saving mode to apply required voltage with low potential to the input buffer, the decoder, the memory array, and the output buffer, thereby saving power.

Abstract: A method for memory device block movement. The method comprises the steps of decoding a block movement command carrying a start address, destination address and move length to generate a block movement signal, generating a first, second and third loading signal when the block movement signal is asserted, receiving the start address, destination address and move length when the loading signals are asserted respectively, during a read cycle, outputting the start address to the memory device to transfer data of a buffer length at a location beginning from the start address in the memory device into a buffer, during a write cycle, transferring the data from the buffer to a location beginning from the destination address in the memory device, subtracting the move length by the buffer length, and adding the buffer length to the start and destination address.

Abstract: A memory device with debug mode. The memory device has a memory unit, a debug mode controller and three buffers. The memory unit accesses desired data according to an address signal and a command signal. The debug mode controller enables the three buffers to buffer address signals, command signals and the corresponding data according to an enable signal from a microprocessor, and detects whether the desired data, the address signal and the command signal change. The three buffers store the desired data, the address signal and the command signal when the desired data, the address signal and the command signal change. The microprocessor may execute a debug analysis according to the address signals, command signal, and the corresponding data stored in the three buffers of the memory device.