Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.

Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.

Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having conductive bumps disposed on a first surface; forming a first adhesion layer and a first carrier board; thinning the wafer; forming a first insulating layer; forming a second adhesion layer and a second carrier board; heating the first adhesion layer to a first temperature to remove the first carrier board and the first adhesion layer; forming trenches; forming a third adhesion layer and a third carrier board; heating the second adhesion layer to a second temperature to remove the second carrier board and the second adhesion layer; forming a second insulating layer filling the trenches; heating the third adhesion layer to a third temperature to remove the third carrier board and the third adhesion layer; and dicing the first insulating layer and the second insulating layer along each trench.

Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.

Abstract: A method of manufacturing chip package is disclosed. The method includes providing a wafer having a first surface and a second surface, in which the wafer includes conductive bumps disposed on the first surface; thinning the wafer from the second surface toward the first surface; dicing the wafer to form chips, in which each chip has a third surface and a fourth surface, and at least one of the conductive bumps is disposed on the third surface; disposing the chips on a substrate, such that the conductive bumps are disposed between the substrate and the third surface, in which any two adjacent of the chips are spaced apart by a gap ranging from 50 ?m to 140 ?m; forming an insulating layer filling the gaps and covering the chips; and dicing the insulating layer along each gap to form a plurality of chip packages.

Abstract: A method of manufacturing chip package is disclosed. The method includes steps of providing a wafer with an upper surface and a lower surface opposite thereto, in which a plurality of conductive pads are disposed on the upper surface; forming a plurality of conductive bumps on the corresponding conductive pads; thinning the wafer from the lower surface towards the upper surface; forming an insulating layer under the lower surface; etching the upper surface of the wafer to form a plurality of trenches exposing the insulating layer; forming a passivation layer covering an inner wall of each of the trenches; and dicing the passivation layer and the insulating layer along each of the trenches to form a plurality of chip packages.

Abstract: A method for manufacturing chip package includes the steps below. A wafer having an upper surface and a lower surface opposite thereto is provided, in which conductive bumps are disposed on the upper surface. The upper surface of the wafer is diced to form trenches. A first insulation layer exposing the conductive bumps is formed on the upper surface and in the trenches. A surface treatment layer is formed on the conductive bumps, and a top surface of the surface treatment layer is higher than that of the first insulation layer. The wafer is thinned from the lower surface toward the upper surface to expose the first insulation layer in the trenches. A second insulation layer is formed below the lower surface. The first and second insulation layers are diced along a center of each trench to form chip packages.

Abstract: A discrete circuit component is made from a substrate with the first and second surfaces thereof each having a corresponding matrix of electrically conductive segments. A plated through-hole connects each of the conductive segments of each the first and second conductive segments electrically. The through-hole is first clogged and then subsequently cleared of clogging in the fabrication stages.

Abstract: A discrete circuit component having an up-right circuit die with lateral electrical connections. The component comprises a substrate having a pair of electrically conductive traces, and a circuit die is planted between the pair of consecutive traces, wherein one electrode of the circuit die on the surface thereof vertical to the substrate is electrically bonded to one of the conductive trace immediately next thereto, while the other electrode of the circuit die on the opposite surface thereof vertical to the substrate is electrically bonded to the other of the pair of conductive traces immediately next thereto. A body of electrical insulation material hermetically seals the circuit die, and a pair of surface electrodes formed on the surface of the body of insulation material are each electrically connected to the corresponding one of the pair of electrically conductive traces extending from the circuit die.

Abstract: A method for fabricating metal bonding for a semiconductor circuit component employing prescribed feed of metal ball is disclosed. The method comprises the steps of, first, placing a metal ball at the metallization site on the surface of the circuit die of the component; then, melting the metal ball on the site; and subsequently solidifying the molten metal and forming a metal bump at the site. A circuit die having formed with one or more metal bumps can then be made into a circuit component featuring stable and reliable electrical leads and suitable to be utilized as large power rating yet with reduced component size in electronic equipment.

Abstract: A discrete circuit component comprises a circuit component die having a first electrode and a second electrode. A surface of a first substrate has an electrically-conductive trace electrically connected to the first electrode of the circuit component die, and a surface of a second substrate also has an electrically-conductive trace electrically connected to the second electrode of the circuit component die. A first terminal electrode is electrically connected to the conductive trace of the first substrate, surface of the first terminal electrode is orthogonal to the longitudinal axis of the conductive trace of the first substrate. A second terminal electrode is electrically connected to the conductive trace of the second substrate, and surface of the second terminal electrode is orthogonal to the longitudinal axis of the conductive trace of the second substrate. The first and second substrates are parallel to each other and encloses the circuit component die.

Abstract: A discrete circuit component comprises a circuit component die having a first electrode and a second electrode. A surface of a first substrate has an electrically-conductive trace electrically connected to the first electrode of the circuit component die, and a surface of a second substrate also has an electrically-conductive trace electrically connected to the second electrode of the circuit component die. A first terminal electrode is electrically connected to the conductive trace of the first substrate, surface of the first terminal electrode is orthogonal to the longitudinal axis of the conductive trace of the first substrate. A second terminal electrode is electrically connected to the conductive trace of the second substrate, and surface of the second terminal electrode is orthogonal to the longitudinal axis of the conductive trace of the second substrate. The first and second substrates are parallel to each other and encloses the circuit component die.