Abstract: A multi-colored dot matrix display device and its controller which has a microprocessor and address buffers, data buffers and video memory planes. Each video memory plane has an associated address buffer and an associated data buffer. A graph control data circuit controls each video plane of memory and a colored pallet to control the display, on the dot matrix display device. The pallet control circuit is used to determine the actual color which is displayed from each video memory plane which controls the final color which is displayed on the dot display device.