Abstract: A method for the directed self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern, the guide pattern having a cavity with a bottom and side walls; forming a functionalisation layer on the guide pattern that has a first portion and a second portion disposed, respectively, on the bottom and side walls of the cavity; forming a protective layer on the first and second portions of the functionalisation layer; etching the protective layer and the second portion of the functionalisation layer such that a portion of the protective layer is retained and the side walls of the cavity are exposed, the retained portion of the protective layer having a thickness of less than 15 nm; selectively etching the portion of the protective layer relative to the first portion of the functionalisation layer and to the guide pattern; and depositing a block copolymer in the cavity.

Abstract: A magnetic tunnel junction with out-of-plane magnetisation includes a storage layer; a reference layer; a tunnel barrier layer, the two magnetisation states of the storage layer being separated by an energy barrier, the magnetic tunnel junction having a thermal stability factor dependent on the energy barrier and on the temperature of use of the magnetic tunnel junction. The storage layer has a thickness comprised between 0.5 times and 8 times a characteristic dimension of a planar section of the tunnel junction; the composition and the thickness of the storage layer are chosen such that the absolute value of the derivative of the thermal stability factor compared to a characteristic dimension of a planar section of the tunnel junction is less than 10 nm?1.

Abstract: A method for correcting deformations of the surface of an object equipped with a device for correcting deformations, the device including a piezoelectric layer including first and second surfaces, a first plurality of electrical tracks arranged on the first surface, a second plurality of electrical tracks arranged on the second surface, the tracks of the first plurality forming a plurality of lines and the tracks of the second plurality forming a plurality of columns, each column of the plurality of columns being perpendicular to the lines of the plurality of lines, the crossing of a line and a column forming a pixel. The method includes measuring the deformations of the surface; identifying the pixels for correcting the deformations and applying, for each identified pixel, with the line and the column corresponding to the pixel, an electric field greater than the coercive field of the piezoelectric material of the piezoelectric layer.

Abstract: A method for encapsulating an integrated circuit includes: forming first and second electrically insulating supports each having a planar surface, so as to form a recess in the first support with respect to its planar surface, and so as to form, with respect to the planar surface of each of the first and second supports, first and second reliefs, so that the first and second reliefs of the supports interact; forming a first electrical contact in the recess; positioning a chip in the recess; forming a second electrical contact on the second carrier; and superposing the first and second carriers so as to superpose their reliefs.

Abstract: The invention relates to a device for transmission of data on a frequency spectrum divided into a plurality Nf of spectrum fragments (f1, f2) each of which covers a frequency band, the frequency bands being discontiguous. The device comprises a packet generator configured to generate a data packet comprising a payload and at least one occurrence of a constant envelope signalling sequence. Said sequence, for example a modified Zadoff-Chu sequence, comprises N complex symbols and consists of a plurality of complex symbol sets each associated with one of the spectrum fragments. Each set comprises N/Nf complex symbols and each complex symbol of a set comprises a scaling term to the frequency band covered by the spectrum fragment associated with this set and a spectral transposition term in the frequency band covered by the spectrum fragment associated with this set.

Abstract: The invention relates to a process for manufacturing a microbolometer (10) comprising a sensitive material (15) based on vanadium oxide (VOx) comprising an additional chemical element chosen from among boron (B), carbon (C), with the exception of nitrogen (N), comprising the following steps: i. determining a non-zero effective amount of the additional chemical element (B, C) starting from which the sensitive material (15), having undergone exposure to a temperature Tr for a duration ?tr, has an electrical resistivity ?a|r at ambient temperature greater than or equal to 50% of the native value ?a of said sensitive material (15); ii. producing the sensitive material (15) in a thin layer having an amount of the additional chemical element (B, C) greater than or equal to the effective amount determined beforehand, the sensitive material being amorphous and having an electrical resistivity of between 1 and 30 ?.cm; iii.

Abstract: A device includes first and second electrodes that are at least partially transparent in a spectral domain; an electroluminescent layer that lies between the first and second electrodes suitable for emitting electromagnetic radiation in the spectral domain, the electromagnetic radiation being circularly polarized in a first polarization direction; a structured substrate, the first electrode lying between the structured substrate and the electroluminescent layer, the structured substrate including features that are reflective in the spectral domain, and that possess a hollow geometric shape configured so that electromagnetic radiation that passes through the first electrode is reflected from the reflective features while preserving the first polarization direction, a filler material that is transparent in the spectral domain and that is arranged to fill the reflective features so that the structured substrate has a planar surface.

Abstract: An electronic chip includes at least an electronic circuit disposed on a front face of a substrate; and an embrittlement structure comprising at least blind holes, each extending through a rear face of the substrate and a portion of the thickness of the substrate and each having a section, in a plane parallel to the rear face of the substrate, of surface area S and having a closed outer contour, the shape of which includes at least one radius of curvature R, such that S>?·R2.

Abstract: A method for encapsulating a microelectronic device, arranged on a support substrate, with an encapsulation cover includes, inter alia, the following sequence of steps: a) providing a support substrate on which a microelectronic device is arranged, b) depositing a bonding layer on the first face of the substrate, around the microelectronic device, c) positioning an encapsulation cover on the bonding layer in such a way as to encapsulate the microelectronic device, d) thinning the second main face of the support substrate and the second main face of the encapsulation cover by chemical etching.

Abstract: A method and device are provided for determining a mode of detection of an element that reflects ultrasonic waves, wherein it comprises at least the following steps: For each point P of a given volume Zr, determining an ultrasonic field value Aijm (P) for N emitter-receiver pairs (i, j) and for one detection mode m, computing a number C m ? ( P , n ? ) = ? i , j = 1 N ? ? c ij m ? ( P , n ? ) of reflections of the wave where c ij m = { 1 if ? ? ? n ? ij m ? ( P ) · n ? ? = 1 0 if ? ? not with {right arrow over (n)}ijm(P) the normal formed by the “forward” direction {right arrow over (d)}i and the “backward” direction {right arrow over (d)}j of the ultrasonic wave emitted and reflected by the reflecting element, computing the energy value Em(P,{right arrow over (n)}) for each point P of the zone Zr, with {right arrow over (n)} and for a plurality of modes m with E m ? ( P , n ? ) = ? i , j = 1

Abstract: A method for forming a functionalised guide pattern, includes forming a functionalisation layer on a substrate; depositing a protective layer on the functionalisation layer; forming a guide pattern on the protective layer that has a cavity opening onto the protective layer and a bottom and side walls; implanting ions with an atomic number of less than 10 in a portion of the protective layer located at the bottom of the cavity, such that the implanted portion can be selectively etched relative to the non-implanted portion; forming, in the cavity, a second functionalisation layer having first and second portions disposed on, respectively, the protective layer at the bottom of the cavity and the side walls of the cavity; and selectively etching the implanted portion and the first portion of the second functionalisation layer, to expose a portion of the functionalisation layer located at the bottom of the cavity.

Abstract: A method for implementing a scanning electron microscopy characterisation technique for the determination of at least one critical dimension of the structure of a sample in the field of dimensional metrology, known as CD-SEM technique, includes producing an experimental image; from a first theoretical model based on parametric mathematical functions, calculating a second theoretical model U(Pi,ti) describing the signal measured at the position Pi at the instant ti, the second model U(Pi,ti) being obtained by algebraic summation of a corrective term S(Pi,ti); determining the set of parameters present in the second theoretical model; wherein the corrective term S(Pi,ti) is calculated by summing the signal coming from the electric charges deposited by the primary electron beam at a plurality of instants t less than or equal to ti.

Abstract: An integrated circuit and a method of securing the integrated circuit during its fabrication. The method includes delimitation of the integrated circuit into a first zone called a standard zone and a second zone called a security zone, and random degradation of an interconnection structure of the security zone thus forming a physical unclonable function modelled by random electrical continuity that can be queried by a challenge-response authentication protocol.

Abstract: A method for projecting a particle beam onto a substrate, the method includes a step of calculating a correction of the scattering effects of the beam by means of a point spread function modelling the forward scattering effects of the particles; a step of modifying a dose profile of the beam, implementing the correction thus calculated; and a step of projecting the beam, the dose profile of which has been modified, onto the substrate, and being wherein the point spread function is, or comprises by way of expression of a linear combination, a two-dimensional double sigmoid function. A method to e-beam lithography is also provided.

Abstract: A 3D microelectronic device is provided with several superimposed layers of components, with an upper layer including one or several memory cells having a SRAM structure and provided with a rear biasing electrode. The biasing of the rear biasing electrode is modified to switch the memory cells from a ROM operating mode to a SRAM operating mode.

Abstract: The invention relates to a method for manufacturing a first support (100) for forming, in particular with a functionalised second support (200), an optoelectronic component (1), the first support (100) comprising a semiconductor layer (110) and an alignment mark (140) provided on said semiconductor layer (110). The manufacturing method includes in particular a step of forming an aperture (141) in a semiconductor layer (110) comprising cadmium, a step of diffusing cadmium in a second location (142) of the aperture (141) and a cadmium sensitive etching step for promoting etching of one from the second location (142) which is rich in cadmium and the rest of a surface (110B) of the semiconductor layer (110). The invention also relates to a first support (100).

Abstract: A method for manufacturing a light-emitting diode is provided, including the following steps in succession, while maintaining a substrate in a vapour-phase epitaxial growth chamber: epitaxial deposition, with an atmosphere having a first non-zero concentration of ammonia in the chamber, of a first GaN alloy layer P-doped with magnesium; epitaxial deposition, on the first GaN alloy layer, of a sacrificial GaN alloy layer in a second atmosphere in the chamber that is not supplied with magnesium; placing the second atmosphere inside the chamber under conditions with a second concentration of ammonia that is at least equal to a third of the first non-zero concentration so as to remove the sacrificial GaN layer; and then epitaxial deposition of a second N-type doped GaN alloy layer so as to form a tunnel junction with the first GaN alloy layer.

Abstract: The invention relates to a method for laser welding a first component to a second component, comprising: placing the first component on the second component; applying a welding mask comprising a flat contact surface to the first component to press the first component onto the second component, the welding mask comprising a through-passage for a laser beam, defining a welding area on the first component, the contact surface at least partially surrounding said passage; emitting a laser beam by a head into the passage of the welding mask, to form a weld bead joining the first component to the second component in the welding area; wherein the welding mask is rigid and rigidly joined to the laser head and the focal length of the laser is constant, the constant focal length being ensured by the rigid mask.

Abstract: Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets NW, width WW,i, of the nanowire/nanosheet number i, i being an integer from 1 to NW, thickness of the nanowire/nanosheet HW,i, number i, i being an integer from 1 to NW, corner radius RW,i of the nanowire/nanosheet number i, i being an integer from 1 to NW, RW,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ?T given by ?T=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowire

Abstract: A microelectromechanical structure with electrothermal actuation including a fixed part, a moveable part, a first electrothermal actuating beam enabling an electric current to flow from the fixed part to the moveable part and a second electrothermal actuating beam enabling an electric current to flow from the fixed part to the moveable part, the beams being mechanically connected to the moveable part enabling a displacement of the moveable part by electrothermal actuation, an electrically conductive connecting element connecting the moveable part to the fixed part, a first connector for connecting the first actuating beam to a first polarisation source and a second connector for connecting the second actuating beam to a second polarisation source, such that the first and the second can be polarised differently and separately.