Abstract: The present description relates to a light emitting and receiving device including:-a light-emitting diode including a first active layer, a first electrode in contact with the lower face of the first active layer, and a second electrode in contact with the upper face of the first active layer; and opposite the light-emitting diode, on an emission face of the light-emitting diode, a light conversion and detection element comprising a second active layer, a third electrode in contact with the lower face of the second active layer, and a fourth electrode in contact with the upper face of the second active layer.

Abstract: A method for manufacturing a power electronic device including the following successive steps: a) providing a silicon semiconductor substrate, the substrate having a front face and a rear face, opposite the front face; b) forming, by epitaxial growth from the front face of the substrate, a first continuous layer of at least one nitrided transition metal coating the front face of the substrate; and c) forming, on the first layer, by epitaxial growth from the front face of the substrate, at least one second layer of a III-V material, preferably III-N.

Abstract: An optoelectronic device including a light-emitting diode covered with a photoluminescent conversion layer based on a perovskite material.

Abstract: A device for acquiring a 2D image and a depth image, including: a first sensor formed in and on a first semiconductor substrate and including regions of a material distinct from that of the substrate located in an interconnect stack in line with 2D image pixels of the first r sensor; and adjoining the first sensor, a second sensor formed in and on a second semiconductor substrate and including a plurality of depth pixels located opposite the regions of the first sensor, wherein each region includes a first portion having, in top view, a smaller surface area than that of a second portion, the material of the regions having an optical index greater than or equal to that of the material of the substrate.

Abstract: A phase change memory cell including: a first layer in a phase change material; a heating element located under the first layer; a second insulating layer coating a side of the heating element; and first stack comprising a third encapsulation layer coating the side faces of the second layer and a fourth encapsulation layer coating the third layer and being in a material having a lower density than that of the material of the third layer.

Abstract: A phase change memory cell including: a first layer in a phase change material; a heating element located under the first layer; a second insulating layer coating a side of the heating element; and a third insulating layer interposed between the first and second layers, in a material having a density higher than that of the material of the second layer.

Abstract: A method of forming nanowires, including the forming on a metal region of a layer having through openings, and the forming in the through openings of portions deposited in a chemical bath, forming all or part of the nanowires and extending from the metal region.

Abstract: A nanowire forming method, including the forming of a DNA origami having through openings, and the forming in the through openings of portions forming all or part of the nanowires.

Abstract: A method of training an artificial neural network, the method comprising: initially training a first artificial neural network with first input data and first pseudo data, wherein the first pseudo data is or was generated by a second artificial neural network in a virgin state, or by the first artificial neural network while in a virgin state; generating second pseudo data using the first artificial neural network, or using the second artificial neural network following at least partially transferring knowledge from the first artificial neural network to the second artificial neural network; and training the first artificial neural network, or another artificial neural network, with the second pseudo data and second input data.

Abstract: A light-emitting diode manufacturing method, including the successive steps of: a) forming an active layer including a stack of multiple quantum wells, each quantum well including a layer made of a semiconductor alloy; b) forming a trench for singularizing the diode, the trench crossing the active layer; and c) applying to the sides of the active layer, at the level of the lateral walls of the trench, a chemical treatment capable of etching a first component of the semiconductor alloy selectively over at least another component of the semiconductor alloy, wherein the bandgap width of the semiconductor alloy is a function of the concentration of the first component in the alloy.

Abstract: A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

Abstract: A method of generating training data for transferring knowledge from a trained artificial neural network to a further artificial neural network, the method including: a) injecting a first sample into the trained artificial neural network; b) reinjecting a pseudo sample, generated based on a replicated sample present at the one or more outputs of the trained artificial neural network, into the trained artificial neural network in order to generate a new replicated sample; and c) repeating b) one or more times, wherein the training data for training the further artificial neural network includes at least two of the reinjected pseudo samples originating from the same first sample and corresponding output values generated by the trained artificial neural network.

Abstract: A method of communication between a first electronic circuit and second electronic circuits via a bidirectional bus allowing the full duplex communication. Each second electronic circuit has a single identifier corresponding thereto. The method includes the transmission by the first electronic circuit of first frames over the bus to the second electronic circuits, the bits of each first frame being distributed in successive groups of bits, a first group of bits corresponding to a first identifier among the identifiers, a second group of bits corresponding to orders to be executed by the second electronic circuit corresponding to the first identifier, and a third group of bits corresponding to a second identifier among the identifiers, only the second electronic circuit corresponding to the second identifier being authorized to transmit a second frame to the first electronic circuit over the bus.

Abstract: An electronic device including semiconductor region located on a gallium nitride layer, two electrodes, located on either side of and insulated from the semiconductor region, the electrodes partially penetrating into the gallium nitride layer, and two lateral MOS transistors formed inside and on top of the semiconductor region.

Abstract: A method of manufacturing an optoelectronic device including-light-emitting diodes comprising the forming of three-dimensional semiconductor elements made of a III-V compound, each comprising a lower portion and an upper portion and, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor area of the III-V compound covering the active area. The upper portions are formed by vapor deposition at a pressure lower than 1.33 mPa.

Abstract: A circuit, intended to be associated in series with a load to be powered including a first field-effect transistor; at least one second field-effect transistor, associated in parallel with the first transistor; and at least one sensor of information representative of a current transmitted to said load, the gate of the second transistor being coupled to an output of the sensor.

Abstract: A blood glucose regulation system including a processing and control unit configured to implement an automated blood glucose regulation method, wherein the regulation method takes into account at least one hyperparameter having a default value, the value of said at least one hyperparameter being adjustable on the fly by the processing and control unit by means of an adjustment function, and wherein the processing and control circuit is configured to, after a regulation period: estimate the performance of the regulation method by means of at least one performance indicator; and adjust on the fly the value of said at least one hyperparameter according to said at least one performance indicator.

Abstract: A method of determining, for each cell of a battery of series-coupled cells, an indicator QCi representative of the charge stored in the cell, this method comprising: a) at the end of a phase of partial discharge or charge of the battery, measuring the voltage Ui across each cell of the battery; b) calculating, for each cell, an interpolation coefficient Xi from a value C_rate representative of the discharge or charge rate of the battery during said partial discharge or charge phase, and from the voltages Ui measured at step a); and c) determining, for each cell, from the interpolation coefficient Xi calculated for the cell at step b) and from a quantity Qcm representative of the charge stored in the battery, said indicator QCi representative of the charge stored in cell.

Abstract: A transistor comprising a gallium nitride layer having a first gate electrode partially penetrating into it, having: a first side coated with a first thickness of a first insulating material and of a second insulating material; and with a second thickness of a conductive material; and a bottom coated with a third thickness, smaller than the first thickness, of the first insulating material.

Abstract: A method of manufacturing an optoelectronic device including light-emitting diodes comprising forming three-dimensional semiconductor elements, extending along parallel axes, made of a III-V compound, with a polarity of the group-III element, the method further including, for each semiconductor element, forming an active area covering the semiconductor element and a stack of semiconductor layers covering the active area, the active area being formed by vapor deposition at low pressure and comprising quantum wells separated by barrier layers, each quantum well including a ternary alloy having at least one first group-III element, the group-V element, and a second group-III element, the ratio of the atomic flux of the group-III elements to the atomic flux of the group-V element is in the range from 1 to 1.8.