Abstract: The invention relates to a process for fabricating a semiconductor diode (1) via transfer of a semiconductor stack (20) then local etching to form a semiconductor pad (30), the production of the semiconductor pad (30) comprising a plurality of sequences comprising a dry etch that leaves a residual segment (23.1; 22.1), formation of a hard-mask spacer (42.1; 43.1), then a wet etch of the residual segment (23.1; 22.1).

Abstract: A microfluidic component used for measuring electrical impedance across a biological object, the component including a microfluidic space including a zone referred to as measurement zone, at least two electrodes arranged facing one another on each side of the measurement zone, the component being formed by assembling, along a longitudinal junction plane, at least two superposed layers referred to as lower layer and upper layer, the two layers each having at least one cavity, the two layers being assembled with one another in such a way as to position the two cavities facing one another in order to form the microfluidic space.

Abstract: An optoelectronic device including a substrate having opposite first and second surfaces; insulation trenches extending through the substrate, surrounding portions of the substrate and electrically insulating the portions from each other, each insulation trench being filled with at least one electrically insulating block and a gaseous volume or being filled with an electrically conductive element electrically isolated from the substrate; at least one light-emitting diode resting on the first surface for each portion of the substrate, the light-emitting diodes comprising wired, conical, or frustoconical semiconductor elements; an electrode layer covering at least one of the light-emitting diodes and a conductive layer overlying the electrode layer around the light-emitting diodes; and a layer encapsulating the light-emitting diodes and covering the entire first surface.

Abstract: A method of forming an opening in an insulating layer covering a semiconductor region including germanium, successively including: the forming of a first masking layer on the insulating layer; the forming on the first masking layer of a second masking layer including an opening; the etching of an opening in the first masking layer, in line with the opening of the second masking layer; the removal of the second masking layer by oxygen-based etching; and the forming of the opening of said insulating layer in line with the opening of the first masking layer, by fluorine-based etching.

Abstract: The present description concerns a method of controlling at least one switch (TH), including: the reception of signals (S3-i) having between one another at least one phase shift representative of a desired state of said at least one switch; the obtaining, from said signals, of a value (Si) representative of the desired state; and the application of the representative value to said at least one switch.

Abstract: A method for optimizing user equipment wireless localization using K reconfigurable intelligent surfaces reflecting signal(s) transmitted between a base station and the user equipment, the method including, whatever an a priori position of the user equipment selecting at least one reconfigurable intelligent surface to activate among the K reconfigurable intelligent surfaces, determining phases of elements of the at least one reconfigurable intelligent surface, by minimizing a predetermined cost function, depending on the a priori position, and accounting for a predetermined position error bound of the user equipment, while ensuring that at most K reconfigurable intelligent surfaces are selected, ensuring that the minimum Euclidian distance between two consecutive selected reconfigurable intelligent surfaces of a predetermined configuration, is strictly higher than a predetermined value limiting interference between additional multipath components generated by the at least one reconfigurable intelligent surfac

Abstract: The present disclosure concerns a device including a first switch, a diode, and a passive resistive element electrically in series between conduction and control terminals of the first switch, a terminal of the diode located on the side of the first switch being coupled to a node of application of a potential variable with respect to the potential of said conduction terminal.

Abstract: A method of manufacturing an optoelectronic device including the following successive steps: a) forming, on an integrated control circuit previously formed inside and on top of a semiconductor substrate, a plurality of inorganic light-emitting diodes; and b) depositing an active photosensitive semiconductor layer to fill free spaces laterally extending between the inorganic light-emitting diodes.

Abstract: A Josephson transistor, this transistor comprising a source and a drain each comprising an electric charge reservoir in electrical contact with a semiconductor layer. Each reservoir comprises a lower face and a side face both buried inside the semiconductor layer, The lower face of each reservoir extends mainly in an intermediate plane parallel to the plane of a support, this intermediate plane being located between a lower plane and an upper plane that define the semiconductor layer. The side face of each reservoir extends mainly perpendicular to the plane of the support, this side face facing the corresponding side face of the other reservoir and being separated from this corresponding side face of the other reservoir by a channel located under a gate of this transistor.

Abstract: The present description relates to a method of manufacturing an electronic circuit (30) comprising: a support (32), an assembly site (31) having a first surface protruding from said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly method; and a peripheral area (39) around said assembly site, the assembly site (31) comprising at least one level, each level comprising conductive pads (34) and insulating posts (380) between the conductive pads, said manufacturing method comprising the forming of said at least one level of the assembly site, such that the edges, in at least one direction (X) of the main plane (XY), of each level of the assembly site and the locations, in the at least one direction (X), of the conductive pads and of the insulating posts of the same level are defined in a same photolithography step of said method.

Abstract: A method for producing a superconducting vanadium silicide on a silicon layer includes treating a face of the silicon layer in order to prepare it for a deposition of vanadium silicide, then depositing a vanadium silicide layer on the prepared face of the silicon layer in order to obtain a stack of a vanadium silicide layer directly deposited on the silicon layer, then an annealing the stack which increases the critical temperature of the vanadium silicide deposited. The treating includes an operation of incorporation of argon atoms in the silicon layer through the face of the silicon layer.

Abstract: A method for preparing a powder comprising an intimate mixture of U3O8 particles and PuO2 particles and which may further comprise particles of ThO2 or NpO2. The method comprises: preparing, via oxalic precipitations, an aqueous suspension S1 of particles of uranium(IV) oxalate and an aqueous suspension S2 of particles of plutonium(IV) oxalate; mixing the aqueous suspension S1 with the aqueous suspension S2 to obtain an aqueous suspension S1+2; separating the aqueous suspension S1+2 into an aqueous phase and a solid phase comprising the particles of uranium(IV) oxalate and the particles of plutonium(IV) oxalate; and calcining the solid phase to convert (1) the particles of uranium(IV) oxalate to particles of triuranium octoxide and (2) the particles of plutonium(IV) oxalate to particles of plutonium(IV) dioxide, whereby the powder is obtained.

Abstract: Flexible haptic interface including a chamber containing a non-newtonian fluid and bounded at least partially by a flexible wall the exterior face of which defines a touch surface capable of being touched by a user; a plurality of actuators borne by a flexible carrier and placed so as to transmit a local mechanical excitation to the fluid; and a control circuit connected to the actuators and configured to modulate the signals sent to the actuators in order to mechanically induce a modification of the rheology of the fluid and to generate a haptic sensation perceptible by the user on the touch surface.

Abstract: The present invention relates to a neuromorphic circuit suitable for implementing a neural network, the neuromorphic circuit comprising: lines of words, pairs of complementary bit-lines, source lines, a set of elementary cells, an electronic circuit implementing a neurone having an output and including: a set of logic components, a counting unit, a comparison unit comprising a comparator and a comparison voltage generator, the comparator being suitable for comparing the output of the counting unit with the comparison voltage generated by the comparison voltage generator in order to output a signal dependent on the comparison and corresponding to the output of the electronic circuit which implements a neurone.

Abstract: This method comprises the following steps: a) providing a stack successively comprising: a substrate; a first electrode; a first dielectric layer, having a first electrical strength; a second metal electrode; a second dielectric layer, having a second dielectric strength that is strictly less than the first dielectric strength; a third electrode; the first dielectric layer and the second electrode having a first interface, the second dielectric layer and the second electrode having a second interface; b) etching the stack by bombardment with electrically charged species, so as to define resistive memory cells; the bombardment of step b) being adapted so that electrically charged species accumulate at the first and second interfaces of each resistive memory cell, so as to generate an electric field that is strictly less than the first electrical strength and is strictly greater than the second dielectric strength.

Abstract: A device including: a transfer substrate including electric connection elements; and a plurality of elementary chips bonded and electrically connected to the transfer substrate, each elementary chip including at least one photodetector and an electronic circuit for reading from the at least one photodetector, the device further including, associated with at least one elementary chip, an emission, capture, or actuation element external to the elementary chip, bonded and electrically connected to the transfer substrate, each elementary chip including an electronic circuit for controlling the emission, capture, or actuation element associated with the chip.

Abstract: An optoelectronic device manufacturing method, including the following successive steps: transferring an active inorganic photosensitive diode stack on an integrated control circuit previously formed inside and on top of a semiconductor substrate; and forming a plurality of organic light-emitting diodes on the active photosensitive diode stack.

Abstract: The present description concerns a method of controlling a bidirectional switch (200), including: first (210 1) and (210 2) field-effect transistors electrically in series between first (262 1) and second (262 2) terminals of the bidirectional switch; third (614) and fourth (612) field-effect transistors electrically in series between said first and second terminals of the bidirectional switch, a first connection node (252) in series with the first and second transistors being common with a second connection node (616) in series with the third and fourth transistors, including steps of: receiving a voltage (V200) between the terminals of the bidirectional switch; detecting, from the received voltage, a first sign of said voltage; at least while the first sign is being detected, coupling the first terminal to said first node (252), potentials of control terminals of the first, second, third, and fourth transistors being referenced to the potential (REF) of the first and second nodes having common sources of th

Abstract: A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.

Abstract: A dissymmetric RN,N-dialkylamides of formula (I) in which: R1 represents a linear C1 to C4 alkyl, R2 represents a linear C1 to C10 alkyl, and R3 represents a linear or branched C6 to C15 alkyl, where R3 is different from a n-octyl, n-decyl, n-dodecyl, 2-ethylhexyl and 2-ethyloctyl group when R1 represents a n-butyl group and R2 represents an ethyl group. A method for synthesising the N,N-dialkylamides, and uses of same for extracting uranium and/or plutonium from an aqueous acid solution or for fully or partially separating the uranium from the plutonium contained in an aqueous acid solution and a solution resulting from the dissolution of spent nuclear fuel in nitric acid. A method for treating an aqueous solution resulting from the dissolution of spent nuclear fuel in nitric acid, which allows the uranium and the plutonium contained in the solution to be extracted, separated and decontaminated in a single cycle.