Abstract: The CMOS circuit has n regions (20a) and p regions (32a) formed in a silicon substrate (2). A first mask is produced on the substrate, whose patterns (10a) mask the p regions (32a). A second mask (22a) is formed on the substrate masking the n regions (20a). The first mask, whose sides have in their upper part an inclined profile, can be selectively etched with respect to the second mask. The patterns of the first and second masks are separate and fix between them the location and width of the isolation trenches (24). The trenches are formed by etching the substrate and simultaneous etching takes place of the first mask and the substrate for forming in the upper part (24a) of each trench and in contact with the p regions, sides (26) inclined with respect to the upper surface of the substrate, so that the section of the trenches (24) widens towards said upper substrate surface.

Abstract: The CMOS circuit has n regions (12a) and p regions (28) formed in a silicon substrate (2b). First and second masks are produced on substrate (2b), respectively having first (8a) and second (15) patterns masking the p regions and n regions. These masks can be selectively etched. The first and second patterns define between them the location of the isolation trenches (18) to be produced. The substrate is etched through the masks to form the trenches and simultaneously etching takes place of the first patterns and the underlying substrate in order to form in the upper part of the trenches inclined sides in contact with the p regions, in such a way that the section of trench (18) widens towards the upper surface of the substrate.