Abstract: The invention discloses an extended joint test action group based controller and a method for functional debugging using the extended joint test action group based controller. The object of the invention to lower the power dissipation (dynamic and leakage) but providing the same functionality of the testing and debugging procedures at the same time will be solved by an extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC which comprises at least one scan chain, wherein an external debugger is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller, whereas a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller.

Abstract: An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

Abstract: The invention discloses a method for fast detection scan of NB-IoT signals in networks. The object of the invention to provide a scanning procedure which is reliable and very fast in order to reduce the search time and hence the power consumption will be solved by a method for fast detection scan of NB-IoT signals in a network by applying a higher sampling rate than 240 kHz and observing a received signal at a receive bandwidth around a magnitude wider than the NB-IoT signal bandwidth of 180 kHz, wherein a set of 2M+1 NB-IoT signals each having a different E-UTRA absolute radio frequency channel number (EARFCN) can be observed simultaneously, whereas M is a natural number and 2M+1 indicates the number of concurrently observed channels.

Abstract: A receiver system includes an interface between a radio receiver on a radio frequency (RF)-side and a baseband receiver on a baseband (BB)-side. The receiver includes an antenna for receiving radio frequency signals and an analogue-to-digital converter for converting received analogue signals to digital signals. The digital signals are further processed in the baseband receiver by a digital signal processing unit. The analogue-to-digital converter is a sigma-delta converter, which includes a sigma-delta modulator on the RF-side and a decimation filter on the BB-side. The sigma-delta modulator and the decimation filter are connected only by single-bit in-phase (I) and quadrature (Q) streams output lines.

Abstract: The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample.

Abstract: The invention discloses an extended joint test action group based controller and a method for functional debugging using the extended joint test action group based controller. The object of the invention to lower the power dissipation (dynamic and leakage) but providing the same functionality of the testing and debugging procedures at the same time will be solved by an extended joint test action group (JTAG) controller for testing flip-flops of a register of an integrated circuit (IC) using a design for testing scan infrastructure on the IC which comprises at least one scan chain, wherein an external debugger is connected to the design for testing scan infrastructure via the JTAG controller which is extended by a debug controller, whereas a feedback loop is formed from an output of the scan chain to an input multiplexer of the scan chain which is activated according to the extended JTAG controller.

Abstract: The invention discloses a method for fast detection scan of NB-IoT signals in networks. The object of the invention to provide a scanning procedure which is reliable and very fast in order to reduce the search time and hence the power consumption will be solved by a method for fast detection scan of NB-IoT signals in a network by applying a higher sampling rate than 240 kHz and observing a received signal at a receive bandwidth around a magnitude wider than the NB-IoT signal bandwidth of 180 kHz, wherein a set of 2M+1 NB-IoT signals each having a different E-UTRA absolute radio frequency channel number (EARFCN) can be observed simultaneously, whereas M is a natural number and 2M+1 indicates the number of concurrently observed channels.

Abstract: The invention discloses a transmission scheme for mobile communication devices scheduled in a cell of a network by a base station, whereas a user equipment (UE) powered by a power supply transmits a block of payload information defined by a limited transmission power over a contiguous total transmission time, whereas transmissions of consecutive blocks of payload information of one UE are separated by scheduling gaps resulting from scheduling of UE transmissions by base station.

Abstract: The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample.

Abstract: The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample.

Abstract: An extended joint test action group based controller and a method of use allows easier testing of integrated circuits by reducing the power dissipation of an IC. The extended joint test action group (JTAG) controller tests internal storage elements that form digital units in an integrated circuit (IC) use a design for testing scan infrastructure on the IC, wherein the JTAG controller is extended by an overall reset generator for all digital units of the IC, and a finite state machine controls the overall reset generator. In reset mode the JTAG controller stops the at least one clock module in supplying the digital units that should be reset. It then sets all scan chains in test mode and switches the input multiplexers into reset mode; and then controls the number of shift clock cycles for shifting in the reset value to the flip-flops in the scan chain, respectively.

Abstract: The invention discloses a transmission scheme for mobile communication devices scheduled in a cell of a network by a base station, whereas a user equipment (UE) powered by a power supply transmits a block of payload information defined by a limited transmission power over a contiguous total transmission time, whereas transmissions of consecutive blocks of payload information of one UE are separated by scheduling gaps resulting from scheduling of UE transmissions by base station.