Abstract: An error detector for received pulses, which pulses normally alternately extend in opposite directions. An up-down counter has first, second, third and fourth sequential states. Means is provided for forming an error signal when the counter is in either the first or fourth state. Means is provided for resetting the counter to one of the second and third states after the counter reaches either the first or fourth state. Means is provided for receiving the pulses and for causing the counter to count up a state responsive to a pulse of one direction and for causing the counter to count down a state responsive to a pulse of the other direction.

Abstract: A coin telephone station simulator and condition indicator. Separate tip, ring, and ground input/output conditioners are provided for connection to a telephone system for test. A controllable coin present relay simulator circuit is switchable from a first high impedance condition to a second lower impedance condition in between tip and ground conductors. A coin test switch switches the controllable relay simulator circuit from the first to the second condition. A coin present indicator is provided together with means for energizing the coin present indicator when the simulator circuit is in the second lower impedance condition. Coin collect and coin return indicators are provided. A coin collect and return detection circuit is responsive to first and second electrical signals, of opposite polarity, momentarily and separately applied in between the tip and ground conductors for individually energizing, respectively, the coin collect and coin return indicators.

Abstract: A first-in/first-out memory device has a shift register with a storage capacity of n stages in which data units can be stored, and a modulo-n address counter having one state representing each stage of the shift register. In one embodiment designed for fast data storage, a data unit is transferred to the input of the shift register, during a write mode, and the state of the address counter is advanced for each data unit so transferred; during a read mode, data units are recirculated from the output of the shift register to its input, the shift register is shifted n times, the state of the address counter is advanced n - 1 times, and the data unit appearing at the output of the shift register when the address counter state represents an empty shift register is retrieved.