Abstract: A hydrogen electrode and the method of making the electrodes usable in a fuel cell comprising a perforated nickel foil current collector, the back side of which is sealed with a semi-permeable membrane of polytetrafluoroethylene (PTFE) with a thickness of 50 .mu.m and a pore diameter of 0.2 .mu.m. The front side is sealed with an electrocatalytic layer of about 25 .mu.m thickness. The electrocatalytic layer contains 75%, by weight, catalyst (carbon particles coated with a layer of catalyzing platinum) with a platinum loading of 0.25-0.6 mg/cm.sup.2. The platinum-covered carbon black is dispersed and embedded as individual but touching granules in strands of PTFE composing 25% of the layer. The porosity of the layer is 80% with a mean volume pore diameter of 10 .mu.m. The strands are obtained by roll compaction of granular PTFE.

Abstract: A serial Viterbi decoder in which a single set of circuits is sequentially used for all the encoder states to calculate the maximum probability path, as measured against received signals, of unencoded signal sequences to reach each encoder state. The path to any encoder state having the maximum probability is traced back to output the oldest encoded signals.

Abstract: In a TDMA satellite communications system with a plurality of transponders and a network of satellite communication controller (SCC) terminals, a data aggregator which may be attached to a local SCC. The data aggregator simultaneously receives TDMA frames from at least two transponders and aggregates locally addressed traffic channels into a TDMA pseudo-frame for delivery to the SCC.

Abstract: A modified Type I decoder generates analog syndrome bits from a selected combination of analog signals representing bits yet to be decoded and digital signals representing already decoded information bits. A selected combination of analog syndrome bits is used to generate a weighted majority decision by analog summation. The weighted majority decision is compared to a variable threshold signal which is proportional to the analog magnitude of the bit being decoded. The decision signal which results from this comparison is used to correct the digital value of the bit being decoded. The required number of analog multipliers is reduced by coupling a plurality of multipliers in series and storing the outputs from different analog multipliers in respective analog storage devices.

Abstract: A variable slope delta coding processor using adaptive prediction in which a digitized signal is transmitted with approximately half the channel bandwidth required by previous techniques without any substantial sacrifice of received signal quality. An estimate of a digital sample is subtracted from a digital sample of an input signal to produce an error signal. The sign bit of the error signal is transmitted as a single bit output signal. A predetermined number of immediately adjacent single bit output signals are utilized to calculate an adaptive step value using a compression technique. A set of reconstructed signal values is built up, one for each of the input signal, with each reconstructed signal value being calculated as the sum of the adaptive step size value and the estimate of the sample of the input signal. For each new sample of the input signal, an oldest reconstructed signal value is discarded and replaced by a newly calculated value.

Abstract: An MSK modulator having a simple construction with only a single necessary adjustment. The digital bit stream to be modulated is fed directly to the control input of a 0,.pi. phase shifter in a single-sideband modulator. A phase shift circuit is used to couple an IF signal to the IF signal input of the single-sideband modulator with the phase thereof adjusted by 0 or .pi. in response to two contiguous bits of the input data stream so as to maintain phase continuity in the output of the modulator for all possible bit combinations in the input stream.

Abstract: An adaptive gain control is provided at the input of a Variable Rate Nearly Instantaneous Companding (VRNIC) processor to adjust the gain of low level speech signals so that the transmission bit rate and SNR will remain substantially the same for low signal levels as for high signal levels.

Abstract: In a secure communications system, a key number which is changed periodically, e.g. monthly, and a random number from a random number generator are combined and used as a seed to reset a PN sequence generator, with the output of the generator being used to control encryption of transmission data in a signal processor. The key is also provided to a first encipherer to encipher the random number for transmission with the encrypted data. At the receiver, the key is provided on common to a decipherer for deciphering the random number and a PN sequence generator which is periodically reset by the combination of the key and random number in the same manner as in the transmitter. The PN sequence is then used to decrypt the information. User identification codes are stored in the transmitter and are used to encipher the key, with each employing its ID code to decipher the key. The user ID codes are known only to the system operator, so that not even a particular user can know the key.

Abstract: A generalized dielectric resonator filter is disclosed for the realization of the most general transfer function characteristics of band-pass filters using cylindrical dielectric resonator discs in a microstrip transmission line configuration. The dielectric resonator filter of the invention has electrical properties comparable to conventional waveguide filters, but has a much smaller volume and mass, and is thus very attractive for use in the construction of input multiplexers of communications satellite transponders.

Abstract: An adaptive equalizer performs equalization at IF, demodulates the input signal and then generates the equalization coefficients at baseband from the demodulated data. Coefficient updating can be done on a non-real time basis and coefficients for individual bursts stored in a coefficient memory for retrieval when the same burst occurs in the next frame, thus obtaining a pseudo-continuous equalization for each burst. The error signal is derived from demodulated equalized data and correlated with demodulated unequalized data to generate the correlation coefficients, and individual error signals from each channel can be combined into a single composite error signal for correlation purposes.

Abstract: Concurrent carrier and clock synchronization are derived from an input signal in interdependent loops without the use of phase look loop (PLL) circuitry in order to improve operation at higher bit rates. An acquisition detection signal is generated only in response to predetermined minimum errors in both the received signal amplitude and the recovered carrier phase.

Abstract: A robust ADPCM encoder with a modified leaky quantizer and a pair of parallel predictors is provided. A large leakage is initially inserted into the quantization scale adaptation by utilizing a number of most recent multipliers in a modified leaky Jayant quantizer. Using a dual predictor feedback loop, inside predictor coefficients are updated by the step size having unit variance instead of by the quantized prediction error.

Abstract: A burst duration and guard space monitor circuit which produces burst duration and guards space signals which are substantially unaffected by nulls or near nulls in a received QPSK signal. The received QPSK signal is compared with a fixed threshold voltage. The comparison output is sampled at twice the symbol rate of the QPSK signal and the samples are first clocked into a three-bit burst duration shift register. The outputs of each of the cells of the burst duration shift register are OR'ed to produce the burst duration signal. The burst duration signal is inverted and then clocked into a four-bit guard space shift register, the outputs of which are OR'ed to produce the guard space signal. A clock signal is produced for operating the flip-flops, burst duration shift register and guard space shift register which has a frequency of twice the clock frequency of the QPSK signal.

Abstract: An apparatus for providing coherent detection of a series of data bursts without a preamble by providing a reference waveform which has the same frequency as the carrier for a received TDMA/MPSK transmission, but having an arbitrary phase with respect to such signals. The reference waveform is used for pseudo-coherent demodulation. Symbol timing is available at all times by using symbol synchronization obtained from the previous bursts of the same transmission. The symbol timing is used to sample two quadrature outputs of the pseudo-coherent demodulator once per MPSK symbol interval. Storage of a sufficient number of demodulator samples allows a carrier phase estimate to be obtained from the message burst itself. The carrier phase estimate is then used for coherent detection on a delayed sequence of the demodulator samples.

Abstract: A phase canceller for a carrier recovery network (CRN) to cancel phase shifts associated with the band pass filter in the network. The canceller is a semiconductor device receiving an input signal at one junction to cause emitted carriers to migrate to a collector at a controlled rate determined by an applied electric field between a pair of ohmic contacts located between emitter and collector junctions with the field control by a signal from a phase detector in the AFC loop of the CRN.

Abstract: The present invention is directed to circuitry for achieving concurrent synchronization of carrier phase and clock timing in double-sideband, suppressed carrier transmissions systems. A phase-lock loop (PLL) is used in the respective carrier and clock recovery networks. The carrier recovery loop is similar to the conventional "Costas Loop". The PLLs are cross coupled in an interdependent recovery structure to enable a more effective clock and carrier regeneration.

Abstract: In a digital echo canceller using an impulse response filter, an interpolating and synchronizing circuit is used to couple the received digital signals from the four-wire circuit to the input of the filter. The interpolation and synchronization circuit generates signals having values between the values of received digital samples, and these interpolated valves are then sampled at the send signal rate and supplied to the impulse response filter.

Abstract: An adaptive delta modulator employs an additional feedback loop to produce a more accurate estimate of the input signal. The delta modulated bit stream is applied to a filter having variable filter characteristics such as bandwidth, the output of the filter being combined with the signal estimated by the prior art adaptive delta modulator. The characteristics of the incoming signal, such as bandwidth, are determined by examining the prior art estimated signal, and the filter characteristics of the additional feedback loop are varied in accordance therewith.

Abstract: A temperature compensated time delay element employs a non-temperature compensated delay element along a first delayed path, and a second non-temperature compensated delay element along a second "undelayed" path to provide a net time delay equal to the difference between the delays in the delayed and undelayed paths. The substrate materials used in the delay elements in the delayed and undelayed paths, and the time delays of the two paths, are selected such that the variation of net phase shift, or time delay, with temperature is zero. The temperature coefficients of the substrate materials in the delayed and undelayed paths can both be positive, thus allowing the use of common substrate materials. The temperature compensated time delay element finds particular utility in differentially coherent signal detection systems.

Abstract: A modulator is disclosed for use with digitized multiplexed voice channels in which service bits are transmitted using QPSK modulation while the audio information is transmitted using amplitude and phase modulation. The audio information in each channel is digitized and compressed using a mapping technique in which zero crossings of the audio signal are represented by binary O. The digitized channels are then multiplexed and coupled to the address inputs of a read-only memory. In the memory are stored digital numbers which represent in quadrature the amplitude and phase of the pulse to be transmitted corresponding to the digital data sample or service word then being presented at the address inputs of the memory. The digital numbers for the control words represent a constant amplitude while those corresponding to the data words represent an amplitude dependent upon the level of the original audio signal. No output carrier is produced for zero-value audio signals.