Abstract: An apparatus for enabling communication of information between processes being carried out on a computing system. Each process is assigned a control block including a specialized memory element. A process being executed modifies the state of each memory element if it discovers any information of interest to processes awaiting execution. Before the next process is executed, the memory element in its control block is tested to find out if the previously-executed process left any information of interest.

Abstract: An information structure called a semaphore serves as a signalling mechanism in process synchronization. The semaphore is used to relate a process and an event which do not appear simultaneously. In accomplishing this, the semaphore is capable of storing the presence of events or resources waiting for processes or, alternatively, the presence of processes waiting for events or resources via a queue.

Abstract: A method of and apparatus for executing a family of instructions provides synchronization of processes in a multiprocessing system. Representations of processes awaiting data (information units) such as the completion of an asynchronous operation or the availability of a resource are stored in a memory in a first queue and representations of information units available to processes are stored in memory in a second queue. Transfer of information units between processes is controlled by data elements known as "semaphores" stored in the memory. Each semaphore contains a field having a numerical value identifying which of the two different kinds of queues is present.

Abstract: Synchronization of processes in a multiprogramming/multiprocessing system is provided by P and V instructions that are executed during execution of processes and operate on data structures known as semaphores which represent processes and events. A process that performs P instruction requests data. The P instruction addresses a semaphore data structure stored in memory. If the semaphore indicates that the data is available, the process continues execution of its next instruction; otherwise, the process is stopped and placed into a wait state until the data become available. A process that performs a V instruction, on the other hand, delivers data to another process. The V instruction addresses a semaphore to determine whether another process is awaiting the data and data are transferred to an awaiting process. If no process is available, the V instruction enables one of the processes in the wait state tied to the same addressed semaphore to be transferred to the ready state.

Abstract: An information structure, or semaphore, serves as a signalling mechanism in process synchronization to connect a process and a non-simultaneously occurring event or resource. The semaphore is a data structure which stores representations of processes awaiting particular events or alternatively stores representations of events awaiting processes. Semaphore data structures are developed in two storage areas. First and second groups of process links are stored in the first storage area to establish, respectively, a first queue of processes ready to operate and a second queue, associated with the semaphore structure, of processes awaiting occurrences of a first particular event prior to being ready to operate. In the second storage area are stored first and second groups of message links to establish respectively a first queue, associated with a semaphore structure, representing second particular events and a second queue of unused links.

Abstract: Apparatus in a data processing system to initialize a semaphore held in a memory field of the data processing system or, alternatively, to restore the semaphore to a previous predetermined state. A count field, or tally field, provided in the semaphore is initialized by a particular instruction. The semaphore can be either a non-message semaphore or a message semaphore. The instruction initializes the semaphore count field of a non message semaphore to zero or a preloaded positive value. For a message semaphore, this instruction initializes the count field to zero. If the message semaphore previously had a positive count, the messages tied to the semaphore are released and the message links holding the messages are transferred to a free message link queue tied to the free link semaphore in the same semaphore descriptor segment.

Abstract: A procedure call mechanism implemented by hardware instructions and a hardware recognizable mechanism known as a stack. A procedure call is utilized by users who have written their programs in a modular way to pass from one program module to another, it is used by user programs to avail themselves of operating system services, and it is used by the operating system itself to achieve a responsive modular structure. The stack is a mechanism permitting the above to be done. A stack is a segment of memory and comprises a number of contiguous portions, known as stack-frames, which are accessed in last in, first out LIFO fashion. Each procedure call creates a stack frame, with subsequent procedure calls creating new stack frames; each exit deletes stack frames thus "popping up" a previous stack-frame. Thus a history of calls is correctly maintained in order to allow a return.

Abstract: Information is selectively exchanged between a number of closely located stations and a number of remote stations. Signals are coupled between the close stations via a first, parallel data channel. A second, serial data channel connects a common adapter circuit for the closely located stations to the remote stations. Each of the stations includes a data module for coupling signals between the first data channel and plural peripheral devices at the station. Each of the modules includes a data processing unit having a memory that stores a program dependent on the configuration of the peripheral devices at the station. Each of the data processing units derives an enabling order for a module at another station, which enabling order is coupled to the another station via the first station or via the first station, the adapter circuit and the second channel; the enabling orders cause the programs stored in the memories to be executed.

Abstract: The disclosure describes improved apparatus and method for implementing the test of various computer functional units interconnected by a common bus. At the beginning of the method, each functional unit is subjected to an enforced condition which disconnects it from the bus. Then, one of the units is subjected to an enforced condition which connects it to the bus and is tested under microprogram control. After the one unit has been tested, another unit is connected to the bus and is tested. In this manner the functional units after first being disconnected from the common bus are reconnected and tested one at a time and those units which have no error detected therein are maintained connected.

Abstract: An arrangement for recording information on a magnetic record carrier, having at least one magnetic recording head which incorporates an electromagnet having a core, wherein said arrangement includes a magnetic shunt, said magnetic shunt and the magnetic core of the electromagnet being adapted to be arranged on either side of said record carrier and close thereto, so as to form a closed magnetic circuit in which the magnetic flux is substantially perpendicular to the surface of the carrier, the said core having a recording pole and a flux-closing pole and the cross-section of the recording pole being smaller than that of the flux-closing pole.

Abstract: A control arrangement for a belt printer having characters arranged in successive series on an endless belt and passed continuously in front of a print support and hammers adapted to be actuated by a control device. A recording store is connected to a calculating unit and records information relating to each character to be printed along a line on the print support. A scan register contains information relating to the coincidences between the characters and the striking members at any given time. Information corresponding to the condition when a predetermined character is to be struck by a given hammer in the course of a given scan, is stored in a storage member along with information indicative of whether or not the predetermined character is repeated in the series of characters.

Abstract: A support for integrated circuit chips to be mounted on an interconnecting base provided with conductive areas. The support consists of a flexible strip made of an inextensible insulating material having equidistant openings towards the center of each of which extend overhanging interface conductors electrically independent of each other. The free inner ends of the conductors in each opening correspond to that of the contact areas on a chip placed at the center of the opening, and each of the conductors has at a point along its overhanging portion, a contact region which is intended to be soldered to a corresponding conductive area on the said interconnecting base.

Abstract: An arrangement for sharing file information among plural processes in a multiprogrammed computing system. Source program file declarations are compiled into file control structures which are placed in skeletal segments, the segments forming units of potential sharing between active processes. Those segments which contain file control structures are placed in either the address space of (1) all processes, (2) related processes, or (3) a single process, depending upon the declared sharing level of the file. Job control language (JCL) commmands are expanded into JCL file control structures and merged with the source language structures to form a file request control structure. This request may be compared against a catalog of existing external files, a check being made to insure that the account on whose behalf a computing job is requesting file assignment is authorized to obtain the requested access to the file.

Abstract: A matching network for distributing high frequency bi-directional signals transmitted along a coaxial transmission line includes a transformer and an active filter having a second order transfer function for coupling a transmitter or a receiver to the transmission line. A comparator comprising trigger-connected differential amplifiers converts the output of the filter to bi-directional signals.

Abstract: A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows:1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU);2. ready -- the process is ready to run as soon as it is given control of the CPU;3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state;4. Suspended -- the process has been temporarily stopped (from a source external to the process).The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Abstract: A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an "ear" are as follows:A. when the process state switches from a running state to a waiting state; orB. when the process state switches from a running state to a suspended state.In both instances the CPU is given away and replaced by the PCB.

Abstract: The disclosure describes an improved apparatus for simultaneously transferring data or commands between several peripheral devices and a central processing unit. The apparatus includes a peripheral control unit which links the central processing unit to several peripheral devices. The peripheral control unit operates as a master with respect to the central processing unit and the peripheral devices in order to increase the capacity of the central processing unit.

Abstract: A multiprogrammable/multiprocessing digital computer system having a process control block for each process in the system, wherein each process control block includes information which specifies the state of a processor at any given time. Associated with each process control block is a decor extension table having information to indicate whether a specified function, such as the emulation of another processor, may be executed in the system. A native mode instruction indicating a specified function for either one instruction or for a plurality of instructions, is first checked to determine proper format, after which a determination is made by means of the decor extension table, as to whether or not the system is capable of executing the specified function indicated by the native mode instruction.

Abstract: Marking apparatus is provided having a reciprocable carrier assembly composed of two parts. One part comprises a motor driven reciprocable carrier, while the other part comprises a movable carrier member which is pivotally supported at one end of the reciprocable carrier. The movable carrier member supports an inking roller and a printing roller and is mechanically coupled to the motor so as to cause the movable carrier member to be positioned, in the course of a first cycle of reciprocation by the reciprocable carrier, such that the inking roller is moved across the entire extent of an impression stamp supported and positioned on a fixed plate, and in the course of a second cycle of reciprocation by the reciprocable carrier, such that the pressure roller is rolled across a document which has been positioned over the stamp between the two cycles of reciprocation. The rolling action of the pressure roller causes the document to be pressed against the stamp to effect the desired marking.

Abstract: The disclosure describes apparatus for handling detected errors in a data processing system. First means define and locate the detected errors and second means allow the attempted reexecution of the instruction being executed when the error is detected.