Abstract: A broadcast center delivers each program in digital form and assembles the digital signals of the programs to constitute a digital multiplex which is conveyed to reception points by radio links or by cables. A program is selected by searching for coinicidence between a user-specified number and a channel number in the digital multiplex. The receiver device comprises an input circuit (1), a synchronization word finding cirucit (2), a bit counter (4), a channel counter (5), a comparator (7), a keyboard (8), first (11) and second (10) registers, a parity check register (13), and a digital to analog converter (14).

Abstract: In a method of selecting one station from a set of stations dialoging with a main station, the main station consults groups of stations one at a time, sending a consultation message to each group consulted. Within each group, stations having information to transmit request reservation of a multiplex link time slot connecting the group to the main station. Each station having information to transmit makes this request after a time delay which depends on the address of the station within the group has elapsed since reception of a synchronization signal. When the main station consults a group, only the station which has reserved this multiplex link can send over the link. In a system implementing this method, each group of stations comprises a self-assigned bus and a synchronization signal link. Each station comprises an assignment system connected to the self-assignment bus and to a microproccessor in the station.

Abstract: The method consists in momentarily replacing the data transmitted by a digital data link with a digital message comprising two non-consecutive sequences, with the first sequence being a prefix sequence and the other sequence being a suffix sequence. The period of time separating the prefix and suffix sequences is variable and encodes remote signalling data. FIG. 2 shows a message transmitter circuit fitted in digital link equipment for operation at a very high data rate, and provided with a circuit (6') for detecting and handing alarms and with a circuit (3) for recovering the bit rate from the digital stream. A pattern generator (10) serves to generate a 1000 pattern and its 0111 complement from the recovered check rate. An oscillator (20) has a period which defines the time interval separating the prefix sequence and the suffix sequence.

Abstract: A digital satellite exchange for connecting analog and digital subscriber lines comprises a digital control unit and subscriber line digital concentrators of at least one of the following types: local analog subscriber line type, remote analog subscriber line type, local digital subscriber line type, remote digital subscriber line type, remote analog/digital subscriber line type. Each concentrator is connected to the control unit by a multiplex link. The control unit concentrates the multiplex links and is connected to a digital subscriber exchange by a further multiplex link.

Abstract: An adapter terminal unit is designed to connect to the time-division switching center of which it forms part at least one digital trunk to a standard different to that normally applicable to the digital trunks associated with the switching center. Each adapter terminal unit, equipped with a microprocessor-based control circuit, is connected by a switching matrix to the input/output lines of the switching center's switching matrix. It further comprises a data and signaling transfer device connected to the switching matrix and to a transmitter device and to a receiver device, one at the end of a transmit multiplex link and the other at the end of a receive multiplex link of the digital trunk. In this way the standard changes necessary for exchanges between the digital trunk and the switching center are effected.

Abstract: A synchronous data transmission method uses an MB 1C 1F type binary-binary code in which the binary data to be transmitted is subdivided into successive blocks of M bits complemented when they feature a disparity (marks minus spaces) of the same sign as the data already encoded, to which is added a complement bit indicating if complementing has been applied and a frame bit consisting of a parity bit enabling the subdivision into blocks carried out at the encoding stage to be recovered at the decoding stage. The encoder has at the input a demultiplexer carrying out the subdivision into blocks followed by circuits for computing the word digital sum and parity and the running digital sum, together with an inverter circuit which processes the blocks from the multiplexer and their parity bit under the control of a complementing decision circuit and a multiplexer transforming the encoded binary signal from the inverter circuit into an isochronous sequence to which a frame bit is added.

Abstract: An inverse discrete cosine transform calculation processor, for processing television picture signals, comprises a processor module consisting of four successive stages. The first stage comprises a multiplier associated with a sine and cosine function value store which is connected to one of its input buses. Each of the other three stages comprises an adder/subtracter having two input buses each selectively connected to the output bus of the directly preceding stage or to the output bus of an input register of this stage also loaded from the output bus of the directly preceding stage and which features on the output bus of one of the input registers of the fourth stage an internal loopback bus which with an input bus of the module is selectively connected to the second input bus of the multiplier.

Abstract: The method consists in momentarily replacing the data in a transmitted digital data stream by a remote signalling message which is built up from consecutive sequences, each of which is obtained by repeating a specific binary pattern chosen from a plurality of possible binary patterns which are generated from the second and fourth sub-harmonics of a clock signal at the bit rate of the digital stream, and from logical combinations thereof. FIG. 2 is a circuit diagram of a transmitter circuit for transmitting a remote signalling message. Said transmitter circuit is located in equipments on a very high data rate digital link, which equipments include a circuit (6') for detecting and handling alarms, and a circuit (3) for recovering the bit rate from the digital stream. Divide-by-two circuits (10, 14) and a logic gate (16) serve to generate three kinds of pattern from the recovered clock rate, namely: 0101, 0011, 1000.

Abstract: A discrete cosine transform calculation processor, suitable for compressing a television signal, comprises a processor module consisting of four successive stages. The first stage, the input stage of the module, comprises a first adder/subtracter. The second stage comprises a second adder/subtracter with two input buses each selectively connected to an output bus of the first stage or to an output bus of an input register of the second stage, loaded from an output bus of the first or fourth stage. The third stage comprises a multiplier connected to a cosine/sine function value store and to an output bus of the second stage. The fourth stage, the module output stage, comprises a third adder/subtracter with two input buses each selectively connected to an output bus of the third stage or to an output bus of an input register of this stage loaded from the multiplier.

Abstract: Frame synchronization devices utilize a frame alignment word decoder connected to the outputs of a shift register which receives on its input the received data bit stream. It is clocked by a clock signal generated from a selection of periods of the data bit stream timing signal reproducing a periodic pattern. This pattern is formed by relative bit locations within the duration of a frame certain at least of which are distributed according to the distribution of the bits of an alignment word in a frame and which form groups of the same size regularly distributed over the duration of a frame. This clock signal is generated in the device by a divider which divides by 20 or by 21 which imposes on it a periodic phase skip by the value of one period of the data bit stream timing for as long as the alignment word is not recognized by the decoder.

Abstract: A multi-stage space-division switching network comprises groups of regenerators (RE1 to RE16) connected to input lines and to output lines of the switching network, it further includes groups of regenerators (RS1 to RS16) connected to a first end of intermediate links (LI1 to LI28) interconnecting two stages and groups of regenerators (R3.1 to R3.16) connected to the other ends of the intermediate links. A monitoring device comprises sampling devices (P) connected to the groups of regenerators and to a comparator circuit (CC). A main marker (MQP) receives connection instructions and sampling instructions and transmits these instructions to auxillary markers (MQ) which control the sampling circuits (P) and the switching circuits (C1, C2) of the switching network.

Abstract: An opto-electronic selector having matrix-addressed photodetectors is characterized in that the photodetectors (Ph) are followed by individual amplifiers (PA), each of which is powered at constant voltage by a voltage source under the control of a matrix line selection control (X) and at constant current from a current source proper to said amplifier and capable of being switched on under the control of a matrix column selection (Y), thereby forming a switching cell (C) in conjunction with the associated photodetector. Such a detector may be used in broadcasting programs to subscribers.

Abstract: An optical space-division switching assembly comprises a distribution assembly consisting of a stack of P distribution plates each with N guides which on the one hand, for each plate, are coupled in common to the end face of an optical element assigned to the plate and belonging to a group of P elements and, on the other hand, for the P plates, communicate with the same side of the stack in N rows of end faces, and an optical selection assembly consisting of a stack of N flat rigid opto-mechanical switches each movable between an optical element assigned to the switch and belonging to another group of N elements and the corresponding row of end faces of the guides of the plates and incorporating P guides having first ends assigned to the individual links between these guides and the corresponding optical element and second ends individually assigned to the P end faces of the guides of the plates of the corresponding row. This assembly provides for the broadcasting of P programs to N subscribers.

Abstract: The device comprises, for coupling the accesses of N first elements (fa) with the accesses of N second elements (fp) an distributer assembly (10) constituted by a stack of P flat and rigid distribution plates (11) having N waveguides (h) each coupled to the access of one of the second elements (fp) and a concentrator-selector assembly (20) constituted by a stack of N flat and rigid concentration and selection plates (21) having P waveguides and including an integrated strip (31) of P photodiodes which are coupled to the ends of the P waveguides, said assemblies being assembled to each other to couple the individual waveguides together. It is particularly applicable to optically broadcasting P programs to N subscribers.

Abstract: A mass spectrograph combining one or more magnetic deflections with the action of electrostatic fields, characterized by the fact that the system is circularly symmetrical; by the fact that the ions are injected radially from a source constituted by a heated circular filament and a pair of small ring-shaped magnets which confine the ionizing electrons to the interior or exterior periphery of the analyzer system per se; by the fact that the first pair of deflection magnets of the analyzer system is ring shaped; and by the fact that the selective action of the other fields, in particular the electrostatic fields, is due to the prior dispersion obtained by the first magnetic induction.

Abstract: A print head for direct or indirect electrostatic printing comprises at least one row (21) of electrodes disposed at a regular pitch and organized in n groups (G.sub.1 . . . G.sub.n) per row, together with a counter-electrode (1) constituted of a resistive material extending opposite the electrodes in the row with n+1 conductive tracks defining n resistances in series (R.sub.1 to R.sub.n) and constituting access connections (C.sub.1, C.sub.n+1) thereto for selecting different groups of electrodes.

Abstract: An addressable photodetector array comprises row addressing lines, column addressing lines, an output line and a biasing line common to all the photodetectors. It further comprises a respective addressing circuit associated with each photodetector. The addressing circuit comprises a first transistor, a second transistor, a first series circuit controlling the second transistor and a second series circuit controlling the first transistor and the first circuit according to a signal on a row addressing line and a signal on a column addressing line.

Abstract: A remote surveillance utilizing signalling incorporated in traffic and concerns more particularly digital links using a prohibited configuration code for the line signal. The purpose is to produce a system consisting of periodically incorporating an interrogation identifier containing a prohibited configuration in the line signal at the transmitter terminal, recognizing the interrogation identifiers as they pass through equipment under remote surveillance, modifying one interrogation identifier out of r by equipment that has remote surveillance data to be transmitted, using the interrogation identifiers reaching the receiving terminal intact to determine those time slots occupied by the remote surveillance signal and extracting the identifiers occupying these time slots for decoding the remote surveillance.

Abstract: A data and signaling time slot transfer and processing system for a set of multiplex lines comprises a switching matrix. Its inputs are connected to n multiplex lines by switching matrix input lines. There are m serial communication controllers each connected to an input register and an output register. The outputs of the switching matrix are connected by m output lines to the input registers. Its inputs are connected by m input lines to the output registers. The matrix outputs are also connected by n switching matrix output lines to multiplex lines. A composite clock signal is applied to all the input and output registers. A further clock signal is applied to the controllers, for the purpose of changing the information reception and transmission bit rates, the information having a bit rate of 64 kbit/s and the multiplex lines functioning at 2.048 Mbit/s.

Abstract: A signaling terminal system for the CCITT No. 7 common channel signaling system comprises groups of terminals and a terminal control unit for each group. Each terminal is connected by a bidirectional link to the switching network of a telecommunication exchange. Level 3 of the exchange comprises a central control unit and a main memory. The terminals and the terminal control unit are connected to level 3 of the exchange by a system bus. Within each group, each terminal is connected to the system bus by an access circuit and to the terminal control unit by an interchange circuit. Pairs of terminals may share a common access circuit and a common interchange circuit.