Abstract: Linking addresses of microinstructions contained in a control memory of a microprogrammed data processing system are determined. The system includes storage elements for predetermined signals and an address register. Each microinstruction includes a preparation phase followed by an execution phase. The microinstructions occur in cycles so microinstruction cycle (n+ 1) follows microinstruction cycle n. The microinstruction of cycle n has: (a) a first bit field designating a linking address to the microinstruction of cycle (n+1) unless modified during cycle n, (b) a second bit field selectively designating which storage elements contain signals that can control selected bits of the first field, and (c) a third bit field for selectively enabling changes to be made in the storage elements.