Abstract: A multipoint conferencing system communicates with a first remote digital simultaneous voice and data (DSVD) modem and a second DSVD modem. The multipoint conferencing system has a first DSVD modem adapted to communicate with the first remote DSVD modem and a second DSVD modem adapted to communicate with the second remote DSVD modem. Each DSVD modem has an analog to digital converter and a digital signal processor coupled to the analog to digital converter for receiving data from the remote DSVD modems. The system also has a bridge coupled to the first and second DSVD modems for transferring data between the first and second remote DSVD modems.

Abstract: A combination keyboard and pointing device is incorporated in a portable computer and includes a dielectric base member on a top side of which a spaced series of electrically conductive pad member portions of a capacitance-based proximity sensing system are formed. Manually depressible key members are positioned above the pads. With the sensing system switched to a typing mode, the pads capacitively sense the proximity, velocity and acceleration of a user's fingers depressing their associated keys and output signals useable by the computer to display the character associated with the depressed key. A sensed increased stroke velocity of each manually depressed key may be used to alter the key character image displayed on the screen, for example capitalizing, bolding or underlining the character.

Abstract: Techniques used in obtaining information in parallel from one or more server systems as requested by a client computer system are disclosed. Multiple requests for information from one or more server systems are made in parallel providing information to the client system asynchronously rather than using a sequential synchronous programming technique.

Abstract: A computer which includes modular structures incorporated therein provides enhanced serviceability. In a preferred embodiment, the computer has a chassis, a lid, a front bezel, an option card module, a system board module, a drive module, and a power supply module. The lid secures the option card module within the chassis. The option card module is removable from the chassis without disconnecting fasteners, option boards, or external cables therefrom. The system board module is received in the chassis and is secured therein by the option card module. The drive module has features which enable storage media devices to be conveniently installed therein and removed therefrom.

Abstract: The present invention applies one or more pruning heuristics to the expression, the binding, and/or the substitute during a database query optimization process. The heuristics identify certain rules that can be eliminated by either not applying the rules and/or not implementing the rules for a given expression and context (if any) based upon one or more flow rates of the expression. The pruning heuristics can eliminate the application of rules based upon the flow rates of the binding or substitute, for example.

Abstract: The hinge system for a portable computer for pivotably securing a top cover to a base unit includes a first base unit hinge member for mounting to the base unit. The first base unit hinge member has proximal and distal mounting portions which are angled relative to each other. The proximal and distal mounting portions are each securable to a surface of the base unit for distributing stress exerted on the base unit by the first base unit hinge member. A first pivoting top cover hinge assembly is secured to the first base unit hinge member. The first top cover hinge assembly mounts to the top cover.

Abstract: A cache memory controller in which data processing systems having active power management may efficiently flush a cache during a shut down operation. A cache map divides the cache into a number of blocks and an inclusion bit is stored for each block. The block inclusion bit is set whenever a cache line in the block is fetched. As a result, when it is time to flush the cache during a time critical power management operation, the software need only flush those sections of the cache where the block inclusion bit has been set.

Abstract: A multiplexing apparatus for use in a computer system is disclosed. The multiplexing system is typically designed for multiplexing various sources of video signal inputs for subsequent processing. The multiplexing apparatus includes at least one analog video input connector, but preferably has more than one, a programmable signal connector, and a plurality of video output connectors. The programmable signal connector couples to the analog video input connector and selectively multiplexes the analog video input signal. The plurality of video output connectors are further coupled to the programmable signal connector, and they receive the multiplexed video signal from the analog video input connector for processing through at least a first video stream. Additional video streams are also possible for processing for a single input signal.

Abstract: A method for preventing inadvertent invalidation of data elements in a system having a separate probe queue and fill queue for each central processing unit, is provided wherein a central processing unit stores a clean data element, that would otherwise have been discarded, in a victim data buffer when it is evicted from cache. The central processing unit subsequently issues a clean-victim command to the system control logic when the readmiss or read-miss-modify command, targeting the data element that maps to the same location in cache as the clean data element, is issued. The clean-victim command causes the duplicate tag store to indicate that the clean data element is no longer stored in that central processing unit's cache. While the data is stored therein, the central processing unit cannot issue a probe message that targets that data until the victim data buffer has been deallocated.

Abstract: The present application discloses a system of software distribution in computer manufacturing which manages and distributes software from release by a software engineering group to installation at a remote manufacturing site or testing facility. The distribution system disclosed seeks to overcome the deficiencies of present software distribution systems. In overcoming these deficiencies, the distribution system disclosed contains several innovative features.

Abstract: A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues.

Abstract: A sense amplifier includes cross-coupled n-transistors that provide, from a predetermined time during one sample period to the start of the next precharge period, a path from a discharging internal node to the low supply voltage VSS. The n-transistors provide a discharge path from the time the internal node falls sufficiently below a precharge voltage to cause the transistors to operate differentially, until the time the node is again precharged, regardless of changes in the state of the input signals. The gate voltages of the cross-coupled transistors are controlled by the internal nodes, and the transistors participate in a positive feedback loop that drives the non-discharging internal node to a high supply voltage VDD through a cross-coupled p-transistor that is controlled by the discharging node.

Abstract: An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. The memory transactions are to be processed by the hierarchical memory. A trigger activates the selector based on second state and transaction information. A sampler stores states of the computer system that are identified with the selected instructions while processing the selected memory transactions in the hierarchical memory.

Abstract: A method and apparatus allows users to quickly effect a modal change in an appliance having first and second modes. The apparatus captures a user actuation indicative of a modal change. The user actuation may be a mouse button closure, a keyboard button closure, or a remote control button closure. Upon detecting the user actuation indicative of a modal change, the apparatus detects the current mode for the appliance. Based on the current mode of the appliance, the apparatus cycles to the next mode in a round-robin basis and sets the next mode to become the current mode for the appliance. Further, in setting the next mode, the apparatus displays the next mode of the appliance as a mode change item in a menu list. The apparatus also then requests a second user actuation confirming a modal change.

Abstract: Racks of modules especially useful for retaining disk drives, tape drives, controllers, computers and the like are fabricated via use of tower building blocks. Each block contains a latch arrangement for securing it to another block, a base unit or a cap unit with the latch effecting interlocking of the blocks so as to form a sturdy assembled structure. Power and/or electrical communication lines are provided in each block with power passing through one vertical array of blocks and electrical communications passing through the other so as to reduce the need for shielding one from the other. An arrangement of alignment pins and mating receptacle holes in conjunction with selected placement of sliding latch elements can facilitate proper coupling of blocks which have similar electrical path boards therein. Spring elements contained in the latch configuration can include biasing to overcome tolerance build-up and plastic creep from repeated and long term usage.

Abstract: A network switch including a plurality of network ports for communicating data packets, each port including logic for receiving a backpressure indication and for transmitting a jamming sequence to terminate transmission of a data packet being received. The switch includes a memory for temporarily storing data packets received by the ports, and a switch manager for determining one or more threshold conditions of the memory, for determining if a new data packet being received is to be stored in the memory for transmission by another port, and if so, for providing the backpressure indication to terminate the new data packet if a backpressure signal indicates that a threshold condition would be violated by storage of the new data packet. The jamming sequence is not sent if the packet is not intended to be stored in the switch, so that network devices coupled to a single port may continue to communicate to each other. The remaining ports of the switch are not effected.

Abstract: A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal.

Abstract: A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the network devices. Each network device includes a slave device or a bus master device or both. The bus includes several conductors for state signals for defining four states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to the address. The bus further includes several conductors for data signals for transferring information data depending upon the different states, where the information data includes bus request, slave identification, the address and the data corresponding to the address. Each bus master includes an interface to the bus to step through each of the states for controlling each cycle. Each bus master and slave device includes an identification number with a predetermined priority.

Abstract: A system for time synchronization in a computer cluster is provided. For the system of the present invention a master node sends a SYNC message including a first time stamp to a slave node. The slave node adds a second time stamp and returns the SYNC message to the master node. The master node then adds a third time stamp to the SYNC message. Using the three time stamps, the master node determines if the time clock within the slave node leads or follows the time clock in the master node. The calculation does not depend on the assumption that transmission delays to the slave node are the same as the transmission delays from the node. If the time clocks do not match, the master node sends an INFO message to the slave node informing the slave node of the correct time for clocks within the computer cluster.