Abstract: A computer system capable of booting currently manufacturable CD-ROMs or tapes without altering the ISO standard or requiring special, customized software to perform this function. A CD-ROM developed for booting according to the present invention contains a boot record as defined by the ISO but located at the end of the defined system area. The operating code of the computer scans for a boot record starting at the beginning sector of the CD-ROM and ending at either a default number or the volume descriptor terminator. The floppy disk boot images are contained at the end of the primary volume space and incorporated in the primary volume space, not external to the primary volume space as in the ISO standard. Boot code contained in the boot record determines the size of the volume, and the proper floppy image to be used and then the actual location of the floppy image. Booting of the system then commences using the floppy image.

Abstract: A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write commands currently held in a posted memory write buffer in the bridge execute prior to the appearance of the posted system management interrupt acknowledge signal. In this way, devices on a downstream bus will not be confused by the occurrence of posted memory write transactions into mistaking such transactions for system management mode operations. In this way, both bridges having posted write buffers and the system management mode may be utilized in efficient joint operation.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A secure start-up system for a computer enables a flash memory to be reset in a secured way. Various operations are carried out to make sure that the reset is an authorized one, and to avoid unauthorized, e.g. virus, infiltration. These operations include multiple tests to avoid the probability of the reset being unauthorized. Any one or more than one of the following can be used. Flashing is only authorized when a special flash enable bit is set in the non-volatile memory. This flash enable bit is reset during every startup cycle. Flashing is only authorized from a cold boot as opposed from a warm boot. This minimizes the possibility of a computer routine authorizing flashing by a software reset. Flashing is only authorized from a floppy. This prevents a virus from writing the flashing routine to the boot sector of a non-removable disc. The user is warned prior to flashing, and asked to confirm.

Abstract: A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory subsystem, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

Abstract: A hot-pluggable hard disk drive is supported on a carrier structure for removable insertion into a sheet metal cage structure in a manner such that an SCA connector on the rear end of the drive is releasably mateable with a corresponding backplane connector within the cage. The carrier has a bottom side with opposite side edge portions from which resilient shock-absorbing foot members downwardly project to protect the carrier-supported disk drive from non-operational shock when the bottom of the carrier is inadvertently permitted to downwardly strike a horizontal support surface such as a table or workbench. Upwardly projecting side wall portions of the carrier are positioned generally over the protective feet, on opposite sides of the supported disk drive, and have top side edges downwardly offset from the top side of the disk drive.

Abstract: A reliable and simple means to awaken sleeping computers is to maintain the network interface subsystem at full power, and to filter detected packets so that when desired packets are detected, full power is restored to the entire computer. An interface to connect a computer to a network is provided, where, the computer has a high power state and a low power state, and the computer is capable of normal operation when in the high power state, and the computer is substantially inactivated when in the low power state. A packet is received from the network. The packet is filtered by computing a hash function using at least one byte selected from the packet. A transition is initiated, responsive to a result of filtering the packet, to transition the computer from the low power state to the high power state. A mask may be used to select the at least one byte. Several bytes may be selected by the mask. A first register may be used to hold the mask.

Abstract: A mounting apparatus includes a bracket having plural sides adapted to accommodate a board between the sides. First fasteners on the plural sides of the bracket are disposed to connect the board to the bracket, wherein the fasteners are adapted to vertically restrain movement of the board relative to the bracket. At least one second fastener on one of the sides releasably secures the bracket to a mounting surface. A process for mounting a board on a surface includes the steps of fitting a board onto a bracket having plural sides, fastening the board to the bracket with first fasteners, and engaging a second fastener with a mounting surface. The board may be a printed wiring board or a printed wiring assembly. The plural sides may include left, right, back, and front sides. The sides may be perpendicular to each other. The first fasteners may be clips, screws, or channels found on the inside of the plural sides. A second fastener may also be included, and may be a slot, a clip, or a tab.

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare.

Abstract: A portable computer system having a loudspeaker enclosure defined by a printed circuit board, a keyboard section cover and a gasket. A second enclosure is defined by an existing frame, the keyboard section cover and a second gasket. Advantageously, a loudspeaker mounting system provides positive urging of the speaker with the keyboard section cover and all other openings, such as the grill attachment apertures and any other openings, are sealed to achieve the total enclosure concept for a speaker system for a portable computer.

Abstract: An orifice plate is operatively secured to the open front end of an internally chambered piezoelectric ceramic body portion of an ink jet print head assembly material using an adhesive material. In securing these two components to one another, a layer of the adhesive material is applied to the front end of the print head body and the orifice plate is pressed against the adhesive layer. The ultimate bond strength of the adhesive material is substantially increased by the presence of a spaced plurality of bonding holes formed through the orifice plate and aligned with a spaced plurality of bonding openings extending inwardly through the front end of the print head body. As the orifice plate is pressed against the body, substantial portions of the initially applied adhesive material layer are forced into the aligned holes and openings.

Abstract: A method and apparatus for interfacing with a stateless NFS (Network File System) server. A pseudo-open state is created for a file when a request from a network client for accessing the file is received in a network server. The term pseudo-open data relates to a set of data that is kept in a network server. The pseudo-open describes the state of a file being currently accessed via an NFS server in the network server. The pseudo-open data differs from normal file state data in that it can be created or recreated at will, thus preserving the stateless functionality of the NFS server. Thus, if a request is received at any time and there is no pseudo-open state established for the file, the pseudo-open state will be established or reestablished at that time. If, on the other hand, a request is received for which a pseudo-open state already exists, the overhead of creating the pseudo-open state is avoided, and the existing data is used. The pseudo-open state is stored in a file-system data structure called VNODE.

Abstract: A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and is trained from a truth based predictor connected to the back end of the pipeline. The stored predictor is accessible in one instruction cycle, and therefore provides minimum predictor latency. Update latency is minimized by storing multiple predictions in the front end stored predictor which are indexed by an index counter. The multiple predictions, as provided by the back end, are indexed by the index counter to select a particular one as current prediction on a given instruction pipeline cycle. The front end stored predictor also passes along to the back end predictor, such as through the instruction pipeline, a position value used to generate the predictions. This further structure accommodates ghost branch instructions that turn out to be flushed out of the pipeline when it must be backed up.

Abstract: A computer system including a monitor which mechanically and electrically receives a peripheral device such as a camera. A top surface of the monitor includes a recessed portion into which the peripheral device mounts. A pair of tabs in the recessed portion engage recesses in the peripheral device securely affixing the peripheral device to the monitor. The monitor also includes an electrical connector that automatically mates with a connector on the peripheral device when the peripheral device is mounted in the recessed portion of the monitor, thereby establishing electrical connectivity between the peripheral device and the computer system. The mounting arrangement securely affixes the peripheral device and obviates the need for the user to connect the peripheral device to the computer by way of an external cable.

Abstract: A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.

Abstract: A process and system for improving the display resolution of a video image that is transmitted point-to-point. The process and system function by determining regions on a screen that are of high interest to a viewer and regions on the screen which are of lower interest to the viewer. Regions of high interest to the viewer are transmitted from a video source and displayed on the screen at a higher resolution than those regions of lower interest to the viewer.

Abstract: Apparatus is provided for adapting a computer system having a standard half-height bay to operatively receive multi-purpose bay devices therein. In one described embodiment, an adapter is provided which may be conveniently mounted in a standard half-height bay, but which is configured to accept multi-purpose bay devices. The adapter includes standard drive connectors, and connectors which permit the adapter to be effectively used in systems having features such as circuitry permitting hot-swapping of drives and circuitry for controlling battery charging and/or discharging. The adapter also includes circuitry for automatic selection of a power source to supply power to devices installed therein.

Abstract: A bus interface is partitionable into at least two slices. Each slice interfaces a respective subset of data from a computer device to a system bus. Each slice also receives a corresponding subset of control information and a complete set of address information from the computer device. Moreover, each slice may be implemented on a single integrated circuit chip, which thus handles both data and control functions.

Abstract: The invention is a computer interface with a hardwired button array on the computer chassis for simulating the apparatus of common consumer electronic devices. Each button of the array of buttons is connected to at least two wires, with the depression of a button causing an electrical connection between the corresponding two wires. The voltage on one of these wires is forced to a steady-state logic low, while the voltage on the other wire is allowed to float electrically free. Nonetheless, the second wire is at a steady-state high voltage due to that wire's connection through a pull-up resistor to a voltage source. Upon electrical connection, the wire that is floating free acquires a logic low voltage. In response, a line state detector sends an interrupt signal to a microprocessor, which transitions the voltage on the wires forced to a steady-state logic low from a logic low to a free floating state.