Abstract: A method for permitting access to secured computer resources based upon a two-piece user verification process. In one embodiment of the invention, the user verification process is carried out during a secure power-up procedure. At some point during the secure power-up procedure, the computer user is required to provide an external token or smart card that is coupled to the computer through specialized hardware. The token or smart card is used to store an encryption algorithm furnished with an encryption key that is unique or of limited production. The computer user is then required to enter a plain text user password. Once entered, the user password is encrypted using the encryption algorithm contained in the external token to create a peripheral password. The peripheral password is compared to a value stored in either secure system memory or in memory contained within a secured resource itself. If the two values match, access to the secured resource is permitted.

Abstract: An apparatus controls a signal that indicates to a plug-in component board that it is to be connected to a 64-bit data path in a computer system. The apparatus comprises a timing circuit for receiving a reset signal and providing first and second complementary logical signals in response thereto. A selection switch receives the first and second logical signals as well as a control signal and outputs a third signal as determined by the logical level of the reset signal. A method involves generating first and second complementary signals from a reset signal, selecting between the first complementary signal and a control signal, and outputting a third signal, the logical value of the third signal being determined by the logical value of at least one of the reset signal and the control signal.

Abstract: A combination support and heat sink structure is mounted within a computer housing for pivotal movement between connected and disconnected positions and includes a pair of cooling plates, one air cooled and the other liquid cooled, carried in a spaced apart, parallel opposing relationship. The two cooling plates are movable toward and away from one another and a pair of manually operable spring clip members permit a processor card to be removably sandwiched and clamped between the cooling plates without the use of tools.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: A battery pack which contains an integral bidirectional up/down voltage converter, so that the voltage of the battery does not have to match the voltage of the system power lines at all. Thus a single battery pack can be used in different systems which have different power bus voltages.

Abstract: A method for providing secure registration and integrity assessment of software in a computer system is disclosed. A secure hash table is created containing a list of secure programs that the user wants to validate prior to execution. The table contains a secure hash value (i.e., a value generated by modification detection code) for each of these programs as originally installed on the computer system. This hash table is stored in protected memory that can only be accessed when the computer system is in system management mode. Following an attempt to execute a secured program, a system management interrupt is generated. An SMI handler then generates a current hash value for the program to be executed. In the event that the current hash value matches the stored hash value, the integrity of the program is guaranteed and it is loaded into memory and executed.

Abstract: A universal battery pack in which an internal switch-mode power converter's control circuitry is powered from the battery side of the converter, rather than from the system side.

Abstract: An apparatus handles long latency interrupt signals in a computer which posts I/O write operations. The apparatus includes a posting buffer for posting write operations and circuitry for ensuring that End-of-Interrupt (EOI) write operations (and other interrupt controller directed I/O operations) are properly synchronized to prevent false interrupts from reaching the processor. Upon receipt of the EOI write operation, the apparatus verifies that the posting buffer is empty before it imposes a pre-determined delay to ensure sufficient time for the cleared the interrupt signal to be transmitted over the interrupt serial bus. Next, the apparatus checks the interrupt serial bus for activities. If the interrupt serial bus is idle, the EOI write operation is issued to the interrupt controller. Alternatively, the apparatus waits until the serial bus becomes inactive for two back-to-back cycles before allowing the EOI write operation to be issued to the interrupt controller.

Abstract: A computer system has a bus, a connector for a circuit card, and a clamp configured to selectively prevent removal of the circuit card from the connector when the clamp is engaged. The computer system has circuitry connected to monitor the engagement status of the clamp and to regulate delivery of power to the connector based on the engagement state of the clamp.

Abstract: A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot of a computer system hot-pluggable, wherein a logic gate controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card whereas the other node is coupled to a bus to which the expansion slot is connected. The apparatus operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card from the bus when the system is running or during the powering up of the card.

Abstract: A computer system including a small array of backlit buttons that can be used to control certain computer system functions. Each button includes a built-in backlight which preferably is a light emitting diode ("LED") that allows a user to see more easily the label on the button. Visual feedback that a button is pressed is provided to the user by turning off a button's backlight when the button is pressed. Thus, once the light in a button turns off, the user knows the button has been depressed sufficiently to activate the function associated with the button. In another aspect of the invention, the computer system may enter a low power consumption sleep mode in which most of the computer's functions are disabled. In the sleep mode the backlights in the button array are turned off to further save power. The computer system also includes a telephone answering machine ("TAM") capability which includes a backlit button that allows the user to play back a previously recorded telephone message.

Abstract: A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed.

Abstract: A method and apparatus for providing a programmable device with operational parameters applicable to successive operational environments. According to some aspects, the method includes the steps of programming memory with a common operational code applicable to multiple operational environments, programming memory with a first operational environment dependent code, operating said device in a first operational environment, changing to a second operational environment, adding a second operational environment dependent code, and operating in a second operational environment. According to some aspects, the apparatus comprises a programmable device operating according to a set of operational parameters reprogrammably stored therein.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

Abstract: A laptop computer contains a built-in modem and has a phone jack for connection to a telephone line while the computer is being operated in a stand-alone mode. A docking station into which the laptop computer may be docked allows the combined unit to be operated in a desk-top mode. The docking station may have a full-sized keyboard and display so that the laptop functions as the main computer a user may employ in the office or home. A telephone connection is already in place at the docking station so that the user need not make a phone line connection to invoke the docked mode, but instead merely nests the laptop in the docking station.

Abstract: A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare.

Abstract: A portable computer docking station has incorporated therein a motorized docking/undocking module which is releasably latched to a housing wall portion of the docking station. The module includes a housing within which a small electric drive motor is operatively mounted, with wall portions of the module housing translationally and rotationally restraining the motor body without the use of screws or other separate fastening members. A docking control system, upon sensing the manual placement of a portable computer on a receiving area adjacent the module energizes the module motor which rotates a cammed worm gear portion of the module which is drivingly linked to latching and ejection portions of the module. The motor-driven latching portion of the module connects to the computer and docks it by forcibly drawing it toward the module in a manner mating facing connectors on the computer and docking station.

Abstract: The placement of components on a circuit board may be controlled automatically by creating a group containing two or more types of components to be placed on the circuit board and by developing a placement path by which any component within the group may be placed on the circuit board at any point along the placement path.

Abstract: A signal represented as a matrix of input values is adaptively filtered using a processor with a multimedia extension unit. A plurality of coefficients are loaded into a first vector register and input values are loaded into a second vector register. Next, for each of the coefficients in the first vector register, (1) a single cycle vector multiply-accumulate operation is performed between the selected coefficient and the input values stored in the second vector register and the result is stored in a third register; (2) a partition-shift on input values in the second vector register is then performed and a new input value is then moved into the second vector register. After each of the four loaded coefficients have been processed, the results are saved and the operation is repeated until all input values in the matrix have been processed.