Abstract: A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory.

Abstract: A technique for disambiguating proximate objects within an image is disclosed. In one embodiment, the technique is realized by obtaining an image which is a representation of a plurality of pixels, wherein at least one grouping of substantially adjacent pixels has been identified in the plurality of pixels. Discontinuities are identified in each of the identified groupings of substantially adjacent pixels. Each of the identified groupings of substantially adjacent pixels are divided according to the identified discontinuities. It is then determined if each of the divided identified groupings of substantially adjacent pixels corresponds to an object to be classified.

Abstract: An apparatus and a method to prompt for an administrative password during the boot block process to flash a corrupted ROM image. During a computer system's power-up and initialization, the flash ROM image is examined to determine if the image is corrupt. If so, the computer system executes certain protected code stored in the boot block of the ROM. When the computer system is booted from this boot block, a reduced set of capabilities are needed. One capability according to the invention, is the ability to flash a new ROM image to the corrupted ROM. Once booted from the boot block, the computer system prompts the user for a password preferably by flashing keyboard LEDs. Upon receiving a password, this password is compared to an administrative password stored in non-volatile memory. If the password matches the administrative password, then the computer system enables the ROM to accept a flash ROM image. If the password does not match, the ROM is disenabled, not accepting a flash ROM image.

Abstract: In a computerized method, a moving articulated figure is tracked in a sequence of 2-D images measured by a monocular camera. The images are individually registered with each other using a 2-D scaled prismatic model of the figure. The 2-D model includes a plurality of links connected by revolute joints to form is a branched, linear-chain of connected links. The registering produces a state trajectory for the figure in the sequence of images. During a reconstructing step, a 3-D model is fitted to the state trajectory to estimate kinematic parameters, and the estimated kinematic parameters are refined using an expectation maximization technique.

Abstract: A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.

Abstract: A method places procedures of an application program in a memory in order to maximize performance. The application program is first mapped to non-executable addresses of the memory. A segment of the memory large enough to store the program is allocated as executable. The procedures are then copied from the mapped non-executable addresses to the executable segment as the procedures are executed. The procedures are copied in the order that they are executed.

Abstract: A PCI bus controller which operates according to the PCI clock run protocol, without the complexity of a typical PCI bridge. This provides the power savings of Mobile PCI Clock run without the overhead, cost and complexity of a PCI to PCI bridge. This is accomplished by supplying a clock run controller, which sits on between the upstream PCI bus and a downstream PCI device, monitors traffic on the bus to determine if the PCI device is being actively accessed. If not, the clock to the PCI device is controlled according to the clock run protocol.

Abstract: A method is provided for guiding virtual-to-physical mapping policies in a computer system including a processor and a memory. State information is randomly sampled from selected memory references in a stream of memory references issued by the processor to the memory. Cache hit/miss status, translation-look-aside buffer hit/miss status, and effective virtual and physical memory addresses of the sampled memory references are recorded in a profile record. The recorded information is aggregated by virtual memory address, and a new virtual-to-physical mapping is choosen to reduce cache and translation-look-aside buffer miss rates.

Abstract: A method analyzes memory transaction processed by memories of a computer system. The method selects a set of addresses of the memories. State information from a plurality of consecutive predetermined memory transactions to the selected addresses are recorded while the selected transactions are processed by the memories. The selecting and the recording steps are repeated until a termination condition is reached. Then, the recorded state information is statistically analyzed to estimate statistics of properties of the memory interactions among contexts in the computer system.

Abstract: A web server computer system includes a dispatcher program that processes transaction request messages received from a web browser. The dispatcher program includes a combination of persistent and transient interpreters that are used to process the transaction. The persistent interpreters are maintained in memory for an indefinite period of time and across multiple transactions. One type of persistent interpreter is a master interpreter that is used to coordinate the processing activity. A second type of persistent interpreter is a pristine interpreter that provides relevant context for any application programs required to process the transaction. A transient interpreter is maintained in memory for a finite duration, such as across a single transaction. One type of transient interpreter is a transaction interpreter that is used to process the transaction request message.

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols.

Abstract: Each processor in a multi-processor system includes a process page-table-base register and a system page-table-base register. Each register identifies a different page frame containing a different instance of a top-level subtable in a multi-level page table, and both instances' contents map their respective, different page frames to the same virtual page. A first of the instances, to which the process page-table-base register refers, is used to translate virtual addresses in a process-private range, while the second instance is used for shared-range translation. When a context switch occurs, the content of the process page-table-base register is changed in accordance with the process to whose operation the processor is turning, but that of the system page-table-base register remains unchanged.

Abstract: A computer is provided having a SCSI subsystem and multiple SCSI devices connected to that subsystem. Those devices involve electromechanical motors which require a greater amount of current during times needed to spin-up the motor-driven devices to a steady-state velocity than current needed to maintain that velocity. Each SCSI device includes an inquiry page indicating attributes of that device and whether that device supports fast spin-up. If a device supports fast spin-up, firmware within the computer is activated during ROM POST operations forwards a command to begin a spin-up operation on one SCSI device before the prior device has completed its spin-up operation. In this manner devices which support fast spin-up can concurrently spin-up to their constant velocity value so as to minimize the initialization process of the computer system subsequent to reset or boot-up of the system.

Abstract: A computer system includes a processor, a memory device, at least one expansion bus, and a bridge device coupling the processor, memory device, and expansion bus together. The bridge device preferably includes a memory controller that is capable of arbitrating among pending memory requests, and in certain situations, starting the next cycle while the current cycle is finishing. This allows executing at least two memory requests concurrently, thus improving bus utilization and retrieving and storing data in memory occurs more efficiently. The memory controller can start the next memory cycle during the current cycle when the next memory cycle will result in a page miss and a bank hit to a bank that is not associated with the most recently used (MRU) page. Further concurrent memory request execution is possible when the next cycle will be a page miss and bank miss.

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract: A network switch including a plurality of network ports for receiving and transmitting data, where each port includes at least one statistics register for storing statistics information, such as Ethernet statistical and configuration information. The switch also includes a switch manager, which further includes a memory, retrieval logic for detecting a statistics request signal and for respondingly retrieving the statistics information for storage in the memory, and response logic for asserting a statistics response signal after the statistics information is stored. A processor is coupled to the switch manager through a bus, where the processor asserts the statistics request signal and then detects assertion of the statistics response signal. Upon detecting the response signal, the processor retrieves the statistics information from the memory.

Abstract: A method of limiting, in a digital processor, low-priority utilization of a resource in favor of high-priority utilization of the resource comprises determining a value predictive of high-priority utilization of the resource. Low-priority utilization of the resource is inhibited if the determined predictive value is greater than a threshold. On the other hand, if the predictive value is less than or equal to the threshold, then low-priority utilization of the resource is allowed. In a preferred embodiment, the predictive value is derived by counting the number of actual high-priority utilizations of the resource out of the last N opportunities in which the resource could have been utilized for a high-priority need. Preferably, recent utilizations are given more weight than others. In a preferred embodiment, the resource comprises one of main memory, instruction cache memory, or data cache memory.

Abstract: A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries.