Abstract: A graphics data processing apparatus includes a graphics memory having pixel storage for storing up to a predetermined number of fragment values for the pixel. Each stored fragment value is associated with a fragment of an image that is visible in that pixel. When a new fragment is determined to be visible in the pixel, but all the available fragment values for the pixel are already in use, one of the previously stored fragment values is either replaced by, or combined with the fragment value for the new fragment. The resulting new fragment value is used to determine the color of the pixel. Alternately, if the new fragment is determined to be totally occluded by one or more of the other fragments, the new fragment may be discarded. Z-depth and Z gradient information is stored each fragment.

Abstract: A radio frequency (RF) device for authorizing user access to portions of a computer system. The RF device includes a power supply, processing circuitry that accesses the power supply according to a location of the RF device, and an antenna that transmits communication signals from the processing circuitry to a transponder that is coupled to the computer system. The processing circuitry is configured to operate at a first power level until the communication signals indicate that the location of the RF device is within a first range of the transponder. The processing circuitry is configured to begin operations at a second power level after the RF device is positioned within the first range of the transponder. The processing circuitry is also configured to operate at the second power level until the communication signals indicate that the location of the RF device has moved outside of a second range from the transponder.

Abstract: An intelligent router takes the place of a conventional SCCP relay in a wireless network. The intelligent router automatically provisions and updates subscriber information in a network file.

Abstract: A wireless local area network (LAN) includes various devices, both hard-wired devices and wireless devices that allow communications between the devices and possibly to other devices in other networks, such as private computer networks and the Internet. The present invention allows wireless devices to sense and access various types of wireless networks, including IEEE 802.11a, 802.11b and 802.11g networks. Access to the wireless networks can be made with or without user intervention. The present invention provides an efficient and versatile means for wireless devices to communicate with other devices in a network.

Abstract: A subscriber's prepay balance is provided to a wireless mobile station (e.g., a cellular telephone) for visual display to a subscriber. Preferably, the prepay balance information is retrieved by a prepay application and, rather than be provided to an interactive voice response unit for conversion into an audible message, the prepay balance is provided through the network to the mobile station itself and displayed thereon. The prepay balance can be provided upon registering the mobile station with the carrier's network and/or upon completion of a phone call. In this way, within a relatively short period of time following the termination of a phone call or during registration, the subscriber's mobile station automatically displays the new prepay balance.

Abstract: A rack mounted computer system comprises a plurality of hot replaceable servers and power supplies that are mounted in chassis and assemblies which are coupled together and in which component specific data is stored in cache memory. The cache memory preferably is implemented on a communication module contained in each chassis/assembly. Some, or all, of the rack mounted components include ROM which contains component specific data. Such data includes one or more values specific to that component. The data may include any or all of the following: serial number, part name, manufacturing information, reorder information and physical dimensions of the associated component. By storing the component specific data in cache, less traffic is necessary on the rack's inter-chassis/assembly communication link(s)-the chassis/assembly communication module snoops its cache and, if the data present in cache, provides the requested data from cache to the component.

Abstract: A battery operated computer system implements a power management scheme based on battery behavior. The battery behavior that is monitored as part of the power management scheme may include battery temperature, current, voltage, and/or capacity. In response to one or more of these battery parameters exceeding a threshold, the computer transitions itself to a lower power consumption mode. In so doing, the potential for the battery to shut itself off due to being over-extended (e.g., over current) is reduced.

Abstract: A method of extracting circuit parameters from picosecond-scale photon timing measurements is disclosed. In one embodiment, the method is implemented by a system that comprises a photomultiplier, a data acquirer, and a processing module. The photomultiplier detects photons emitted from current-carrying channels in an integrated circuit, and associates a detection position and a detection time with each detected photon. The data acquirer receives position and time signals from the photomultiplier, and further receives a trigger signal. The data acquirer determines a relative detection time for each photon by combining the time and trigger signals. The data acquirer gradually compiles the photon detection data and makes it available to the processing module. The processing module responsively determines optimal values for a parameterized model of the data. The model is preferably based on non-homogeneous Poisson process statistics, and may employ a maximum likelihood approach to estimating the optimal values.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.

Abstract: A security token is used to dynamically create a user account on a host computer system. The token preferably is programmed with a user's credentials which includes information regarding the user account and security data. Once programmed, the token then can be inserted into a host computer. The user verifies himself or herself to the host computer/token and the token verifies itself to the host computer. Once verified, the user's credentials stored on the token are accessed to dynamically create the user account on the host system. The token may comprise a smart card, USB-compatible memory device, and the like. Storage media, such as floppy disks, also can be used if fewer security features are acceptable.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system with multiple nodes in a transaction order queue (TOQ). Interconnect transactions are dequeued from the TOQ and scheduled for a destination node through a buffer between the TOQ and a scheduler. Interconnect transactions of the first transaction type are blocked from the scheduler until all interconnect transactions scheduled for other nodes in the computer system have completed. No interconnect transactions are dequeued from the TOQ while an interconnect transactions of the first transaction type is blocked from the scheduler. The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol.

Abstract: A system and method for controlling computer resources on an interconnected system via an extensible and dynamic rule set. The extensible and dynamic rule set is capable of both monitoring and modifying the condition and operation of the interconnected system. An editor provides the ability to create, delete or modify the individual rules within the extensible and dynamic rules set. An engine is used to trigger individual rules. A rule may be created, deleted, modified or compiled without the recompilation of the engine. Such rules are triggered when conditions specified in the rule are found to exist on the interconnected system. When such conditions exist, the rule is triggered and the operation of the interconnected system is modified as specified in the rule.

Abstract: An electronic device has a plurality of selectable capabilities. The capabilities may include CPU speed, NIC speed, various protocols, or, in general, any parameters, characteristics or features which a user might desire to have in the electronic device. The device receives a key, such as from an external licensing authority, and the key specifies which capabilities the device should use to configure itself. The user may have to pay the licensing authority for the key. The electronic device thus can be configured into any one of a plurality of capabilities without having to change any hardware—the user simply purchases a key commensurate with a capability desired by the user.

Abstract: A copy protection method and apparatus is provided to inhibit unauthorized viewing or copying of a video signal. A varying set of additional or invalid video pulses are generated onto a typical video signal. A pulse sequence identifier identifies the location of the invalid or additional pulses and is likewise generated onto the video signal prior to the occurrence of the identified pulses. The combined signal is received at an authorized display which then decodes or filters the additional or invalid portion of the video signal from the original signal according to a decode protocol stored in local memory. A resultant video output signal is guaranteed from only the original signal.

Abstract: A cyclic redundancy check (CRC) mechanism for the extensions (PCI-X) to the Peripheral Component Interconnect (PCI) bus system used in computer systems is fully backward compatible with the full PCI-X protocol. CRC check-bits are inserted to provide error detection capability for the header address and attribute phases, and for burst and DWORD transaction data phases. The CRC check-bits are inserted into unused attribute or clock (or target response) phases, or into reserved or reserved drive high portions (bits) of the AD, C/BE#, or into the parity lanes of the PCI-X phases.

Abstract: A server, or other electronic device, includes a handle mated with the server. The server slides into and mates with a chassis. The handle is formed to provide a central opening through which visual and physical access is provided to a portion of the server, and preferably a portion of the server on which user interactive components are provided. Such components may one or more include status indicators, one or more user activated controls and one or more connectors. The opening permits the user to see the status indicators, which may comprise LEDs, activate the controls and connect an external cable to the server. The handle also is mated to the server via a hinge and a locking mechanism. With the locking mechanism is disengaged, the handle pivots away from the server. The user can then grip and further pivot the handle and pull the server out of the chassis.

Abstract: A system for compensating for non-functional ink cartridge ink jet nozzles is provided. The system includes an ink jet compensation system that receives ink jet nozzle failure data, such as each nozzle that is clogged or damaged, and that generates nozzle correction data, such as a nozzle to fire instead of each failed nozzle for a given print pattern or a nozzle firing sequence that compensates for the failed nozzle, such as by printing at that location during a subsequent or previous printer head pass. An ink control system receives the nozzle correction data and image data and generates printer control data, such as by receiving image data in a standard format for printing and modifying the printer control data that would be generated if all ink jet heads were functioning properly to include the nozzle correction data.

Abstract: The specification discloses an alternating current to direct current switching power supply, with power factor correction, and having an integrated rectifying bridge and boost circuit that results in the use of fewer power semiconductor devices in the rectification and boosting process. The use of fewer power semiconductor devices translates into a power supply with greater efficiency and/or smaller size. More particularly, the diodes in a rectifying bridge that typically conduct power back to the alternating current power source are paralleled by power MOSFETs, and the boost inductor is coupled between the source and the modified bridge. Charging of the boost inductor takes place through the power MOSFETs, resulting in only a two MOSFET power dissipation. Discharging of the boost inductor (and therefore supplying power not the load) takes place through two diodes, and therefore two forward power losses (as opposed to three diodes and three forward conduction losses associated in the related art).

Abstract: A computer network comprising a plurality of computing entities including a dynamic provisioning system that redeploys computer systems between resource groups. The determination as to when this transition between resource groups should occur is based on performance statistics gathered from the network. The transition from one group to the other includes, disabling the computer from a first resource group, reconfiguring the computer according to a configuration database, and redeploying the reconfigured machine to a second resource group. The second resource group can be an over utilized resource group that needs extra compute resources or it can be an idle resource group.

Abstract: A cache memory controller allows hot-plug insertion and removal of cache memory modules. After detecting an insertion, the controller waits a predetermined time, then determines the size and speed of the added cache memory modules. If the inserted cache memory module is acceptable, then tag memory is reconfigured to correspond to the inserted memory. The added cache memory is initialized. After successful insertion and initialization, a status bit in the cache controller is set to indicate memory has been added. Prior to removal of a cache memory module, the cache is flushed to main memory and further cache transactions are disabled. After removal of the cache memory module, tag memory is reconfigured to mark a corresponding portion of the tag memory as unused. After successful removal of the cache memory module and reconfiguration of the tag memory, the cache memory controller enables new cache memory transactions.