Abstract: An aliasing technique allows transparently connecting multiple interconnects across a shared cross-connect interconnect, allowing devices on one interconnect to communicate with devices on another interconnect as if both interconnects were connected by a single interconnect bridge. Each interconnect appears to the cross-connect interconnect as a device on the cross-connect interconnect. Transactions between devices on different interconnects are aliased by a routing engine connected to the cross-connect interconnect for transmittal across the cross-connect interconnect and are invisible to other transactions on the cross-connect interconnect. Transactions between devices on the same interconnect are invisible to other interconnects. Cache coherent requests are supported by the use of additional attribute bits.

Abstract: A distributed power management technique allows controlling power states of devices separated from a power management controller, such as a processor, by an interconnect. The power management controller inserts power state information into an interconnect transaction. An interconnect connected device then extracts the power state information and modifies the power state of the device responsive to the power state information. The power state information can be extracted by a processor that then controls the power state of another device responsive to the power state information.

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.

Abstract: A system for controlling a cursor is provided. The system includes a monitored system that generates user interface data and mouse position data, such as would be provided in a monitor window. A remote monitoring system receives the user interface data and mouse control data, such as for controlling the location of a cursor in a local window and a monitor window. A mouse synchronization system receives the user interface data and the mouse control data and generates mouse calibration data based on the user interface data and the mouse control data, such as by determining the actual movement of the mouse using video data and determining a correction factor related to the estimated location of the mouse, based on mouse control data.

Abstract: A computer system is adapted for indicating current operating speeds of a plurality of expansion slots. The computer system includes a set of expansion slot speed indicators to indicate the current operating speeds.

Abstract: A system for characterizing color is provided. The system includes a color patch identification system that receives image data, such as image data of a color wedge, and generates color patch data, such as for two or more patches that make up the color wedge. A color patch characterization system receives the color patch data and generates color density data, such as by calculating the average color density of each color patch.

Abstract: A fail-over system for memory is provided. The fail-over system for memory includes a virtual channel memory controller providing one or more virtual channel memories in a memory array. A memory fail-over controller coupled to the virtual channel memory controller provides memory fail-over data to the virtual channel memory controller. The virtual channel memory controller allocates one or more of the virtual channel memories to one or more fail-over memory channels in response to the memory fail-over data.

Abstract: A battery powered computer system determines when the system is not in use by monitoring various events associated with the operation of the system. The system preferably monitors the number of cache read misses and write operations, i.e., the cache hit rate, and reduces the system clock frequency when the cache hit rate rises above a certain level. When the cache hit rate is above a certain level, then it can be assumed that the processor is executing a tight loop, such as when the processor is waiting for a key to be pressed and then the frequency can be reduced without affecting system performance. Alternatively, the apparatus monitors the occurrence of memory page misses, I/O write cycles or other events to determine the level of activity of the computer system.