Abstract: A circuit for configuring a Plug and Play expansion card in one of three ways. The first is the standard Plug and Play configuration method, wherein expansion cards go through the isolation process to obtain unique Card Select Numbers (CSN). This method requires the existence of a dedicated serial EEPROM to store the system resource data for the expansion cards. However, when an expansion card is directly mounted onto a system board, it becomes a system board device. This allows the separate serial EEPROM to be removed. To implement, two alternative configuration modes are provided, wherein the expansion card can be configured under main CPU control. In these alternative modes, the configuration data is stored in the main system BIOS ROM. In the first mode, a register in the expansion card is mapped to a fixed ISA I/O address. In the second mode, the register is controlled by a dedicated pin, thus allowing it to be mapped to any ISA I/O address.

Abstract: A battery pack for a computer system including static memory to maintain battery operating parameters and charge information, a real time clock (RTC) for measuring periods of non-use of the battery and a communication circuit to exchange the battery information with a microcontroller located in the computer system. The static memory, RTC and communication circuit is preferably in the form of a single RAM/RTC chip. The battery pack also includes circuitry to maintain power to the RAM/RTC from the battery if AC power is not available. The microcontroller detects the presence of the battery and retrieves the present time from the RTC, a timestamp indicating time or removal of the battery and other operating parameters and charge information from the battery pack, and controls the charging functions of the battery accordingly. The microcontroller also updates the charge information of the battery pack while performing other housekeeping functions of a DC--DC converter.

Abstract: A technique for minimizing heat-induced chipside solder joint fractures involving BGA (Ball Grid Array) components mounted on a multilayer printed circuit board when the board is passed through a wavesolder oven. The technique involves shielding the chipside solder joints from the effects of conductive heating by covering the through vias positioned underneath the BGA components with an insulating material. The insulating materials include silk screen material, solder mask and KAPTON tape. During wavesolder, the insulating material blocks conductive heat flow from the exposed board face through the vias and into the BGA component landing areas. With the wavesolder heat flow blocked, the BGA landing areas and BGA components experience much less heat deformation, and a much lower solder joint defect rate is achieved. Selection of silk screen, solder mask or KAPTON tape is based on a balance of solder process conditions and effective insulation capability, with the lowest cost, most effective solution preferred.

Abstract: Applicant's invention includes an apparatus and associated method for transmitting information at a high rate using an undermodulated frequency shift keyed signal. The transmission rate is independent of the data content and the system requires no zero crossing detectors. The demodulator combines non-linear processing circuitry with a conventional demodulator.

Abstract: The top side wall of a portable computer base housing portion has a rectangular opening therein that complementarily receives a keyboard assembly. The keyboard assembly has a rear side edge portion from which a spaced plurality of mounting tabs outwardly project, and a spaced plurality of latch structures are captively retained on a front side edge portion of the keyboard assembly. Each latch structure includes a tab member that is slidable relative to the balance of the keyboard assembly between a forwardly extended position and a rearwardly retracted position, and a cap portion pivotally retained on the tab member.

Abstract: A microcomputer system with a data destination facility provides for accessing dynamic RAMs of different speeds faster or slower depending on the dynamic RAM speed. When the data destination facility maps the dynamic rams, it also saves a bit indicating whether the block of RAM is a high or low speed RAM. When the memory controller attempts to access a certain location, the data destination facility then returns the value of the speed bit associated with that block of memory to the memory controller state machine, which then omits or adds clock cycles to the memory access depending upon the speed of the memory. Further, in setting up the data destination facility, the system initialization routine determines SIMM sizes by first touching the memory locations at which the SIMMs are occupied to determine if there is memory there, and then determines the SIMM speeds based on a combination of the SIMM sizes and the SIMM identification codes returned through a standard serial shift register.

Abstract: A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

Abstract: A video controller uses memory-mapping to address registers in the video controller to enhance speed of the computer system. The memory-map registers may be mapped to a high address area located within the address space of the frame buffer or to a low address area below one megabyte.

Abstract: A system for mapping a PCI interrupt signal to any EISA interrupt signal, in which sharing is allowed between PCI interrupts as well as between a PCI interrupt and an EISA interrupt. The actual mapping is performed during the Power On Self Test (POST) procedure, where the computer writes appropriate values into a set of MAP and MASK registers. Each MAP and MASK register corresponds to a PCI interrupt. Thus, by programming the appropriate MAP and MASK register to certain values, the corresponding PCI interrupt can be mapped to the desired EISA interrupt signal. A decode logic then produces a set of final interrupt signals based on the state of the PCI interrupt signals, the MAP and MASK registers, and the EISA interrupt signals. The final interrupt signals are provided to an interrupt controller, which responds to the assertion of the final interrupt signals by asserting an interrupt signal to the microprocessor.

Abstract: A method for film coated passivation of individual grooves or channels in an array of closely spaced grooves or channels of a workpiece, for example, ink channels in a printhead employed in an ink jet printer device; includes the steps of placing the workpiece on a rotation plate having a rotational center, securing the workpiece to the rotation plate with the grooves directed radially outward from the rotational center of the rotation plate, placing resin upon the workpiece in the vicinity of the grooves, and spinning the rotation plate to cause the resin to migrate along the surfaces of the grooves and thereby coating them.

Abstract: Disclosed are an ink jet printhead and method of manufacturing the same.

Abstract: A method and system for accommodating multiple video controllers. The method includes communicating a plurality of primitive commands to a video controller having a configuration of a predetermined type. Further, the method includes electronically determining the type of the configuration, and generating a vector table comprising a plurality of device-specific routines. Each entry in the vector table may point to a device-specific routine for hardware acceleration of a primitive command or to a default routine which sets the video controller in a specific mode which can be operated by a set of colordepth-specific routines which operate on any video controller set to the specific mode. In response to a primitive from the operating environment, common code, which is device and colordepth independent, will access a routine via the vector table. If the vector table does not access a hardware accelerated routine, colordepth specific code is used to execute the primitive.

Abstract: The orientation of a polarized capacitor is determined by applying a voltage signal to one of the leads of the capacitor and a reference signal to the other lead. The magnitude of the electric field thus generated by the capacitor is measured. Then the voltage signal and the reference signal are reversed. The magnitude of the new electric field thus generated by the capacitor is measured. The ratio of the magnitudes of the first measured electric field to the second measured electric field is computed. If the ratio is greater than one, then the capacitor is determined to be properly oriented. If the ratio is less than one, then the capacitor is determined to be improperly oriented.

Abstract: In accordance with the teachings of this invention, matched performance of alternate sourced ASICs is achieved while still allowing for the smallest die size possible from each alternate source fabrication facility. In one aspect of this invention, the width of electrical interconnects are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In another aspect, transistor channel widths are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In yet another aspect of this invention, capacitance is added to the gates of transistors to decrease their speed, when manufactured by an inherently faster process.

Abstract: A test fixture including top and bottom probe plates including double-ended pogo pins interfacing top and bottom interface printed circuit board (IPCBs), further including double-ended transfer pins to achieve a true wireless dual access test fixture. The top transfer pins electrically engage the bottom transfer pins after vacuum is applied to allow electrical interface with the top-side fixture without the use of wires. The top fixture mounts in a frame assembly through a parallel linkage keeping the top fixture parallel with the PCB under test. Guide pins mounted on the bottom probe plate are used to align a top plate holding the PCB and also to pre-align with bushings on the top fixture before vacuum is applied. When vacuum is applied, the top plate and top fixture move in a single longitudinal direction to electrically engage the test pins and test pads, preventing lateral movement which heretofore caused significant damage to the test pins and test pads.

Abstract: A power switch circuit including a small signal transformer and a low power oscillator for detecting the power switch while isolating it from the primary of the power supply. When the power switch is off, or is otherwise pressed to turn off the power supply, the oscillator charges a capacitor. A sensing and control circuit coupled to the oscillator and capacitor grounds a vital signal of the power supply keeping the power supply turned off. In one embodiment, when the switch is turned on, it shorts the signal transformer disabling the oscillator, so that the capacitor is discharged and the sensing and control circuit releases the vital signal. In another embodiment, the power switch momentarily disables the oscillator and discharges the capacitor, so that the sensing and control circuit toggles a flip-flop circuit to turn on the power supply.

Abstract: Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used.

Abstract: A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.