Abstract: A circuit board carrier has main frame, at least one first holder, at least one slide and at least one second holder. The first and second holders are mounted on and selectively slide on the main frame. The slide is mounted on and selectively slides on the corresponding first holder. The slide has a first pin and the second holder has a second pin. The circuit board is held on the circuit board carrier by the pins. Therefore, the circuit board is kept from being contacted to the delivering wheels during manufacturing and is not polluted and trapped by the delivering wheels.

Abstract: A solder paste stenciling apparatus for minimizing residue of solder paste includes a stencil having multiple stencil openings defined therein, a supporting member retaining the stencil, and a vibrator for vibrating the stencil. In operation, a substrate is engaged to a bottom surface of the stencil, and solder paste is applied onto a top surface of the stencil so that the stencil openings are filled with the solder paste. The substrate is then slowly separated from the stencil while the vibrator vibrates the stencil to evacuate the solder paste out of the stencil openings and to further deposit on the substrate. Hence, the amount of residual solder paste adhered to inner surfaces defining the stencil openings is minimized.

Abstract: A detecting structure formed on the space of circuit unit correctly and easily detects whether the lines of the circuit unit are formed on the correct position, and more particularly to obtain the deviation difference of a position provided to form the lines. The detecting structure is able to be formed on a space of periphery of each circuit unit, thus the detecting result is exactly correct.

Abstract: A method for fabricating a resistor on a printed circuit board (PCB) uses a resistance film material, an exposure process, a photographic negative and a development process to fabricate a resistor on the PCB. The resistance film material has low content of dissolvent to prevent the resistor from shrinking and affecting the resistance of the resistor. The resistance film material has a fixed thickness, so that the thickness of the resistor in the PCB is easily controlled. Furthermore, the method uses an exposure and development process and the negative to from the resistor pattern on the PCB to make the length and width of the resistor pattern very accurate.

Abstract: A method for fabricating a resistor on a printed circuit board (PCB) uses a resistance film material and a dry etching process to form a resistor on the PCB. The resistance film material has low dissolvent content to prevent the resistor from shrinking and affecting the resistance of the resistor. The resistance film material has a fixed thickness, so the thickness of the resistor in the PCB is easily controlled. Furthermore, the method uses a dry etching process to precisely form the resistor on the PCB to make the length and width of the resistor pattern very accurate.

Abstract: A positioning target for a printed circuit board made of base layers and by at least two pressing processes has a first width, a second width formed in the first width, a left margin and a right margin formed on opposite sides of the second width and immediately adjacent to the second width, a first length, a second length formed in the first length, a top margin and a bottom margin. An area formed by a mix of the second width and the second length is for the laminated printed circuit board and multiple positioning holes are respectively defined in two adjacent margins horizontally respective to end sides of two adjacent margins.

Abstract: A method for forming ultra-fine width lines on a substrate avoids occurrence of overetch/underetch defects in the many etching steps, as solder layer or copper film etching steps. With the present method the line shape is able to be achieved close to an ideal shape, so that the quality of the lines is high and the integration of the substrate is also high.

Abstract: A method for making a planar inductor is disclosed. The inductor is made by using a core with high magnetic flux. Outside the substrate, a layer of insulator and conductive foil is securely mounted. Thereafter, copper traces are formed on the insulator. Before the copper traces are formed, holes are defined and metalized to provide electrical connection between conductive foils on opposite sides of the core, which forms a planar inductance. Furthermore, if the copper traces are breaking up in a predetermined location, the planar inductance becomes a transformer.

Abstract: A method is disclosed for determining a side-etching distance to compensate for the width of a wire to be formed on a printed circuit board. The wire is formed on a test board by etching off the copper foil on the test board with a film having the pattern of the wire. The wire is measured to find its resistance. The side-etching distance is obtained based on the formula: W=[(&rgr;/t)×L]×(1/R)±&sgr;, where W is the width of the wire, &rgr; is the resistance coefficient of the copper foil, t is the thickness of the copper foil, L is the length of the wire, and &sgr; is the side-etching distance.

Abstract: A flat, built-in resistor and capacitor has a substrate (10) made of dielectric material; a copper layer (12) formed on each surface of the substrate (10) and having an etched image (30) formed in each of the copper layers (12); a dielectric material layer (40) printed onto the copper layer (12) and filling up the etched image; and a resistance layer (50) printed onto the copper layer (12) and the dielectric material layer (40).

Abstract: A method and structure for packaging an integrated circuit with an encapsulant to be readily peeled away from a degating region is disclosed. By applying an additional processing operation before a solder mask is coated over the substrate or during a process for forming the solder mask, an adhesion between the solder mask and the encapsulant is altered to become weaker than the adhesion between the solder mask and the substrate so that the excess encapsulant can be easily peeled away from the degating region without damaging the substrate.

Abstract: The present invention relates to a TF-BGA method for manufacturing a packaging substrate, and includes steps of forming a single-sided circuit on a copper plate by electroplating, removing a layer of photoresist and sequentially laminating a dielectric layer and a metal plate on the copper plate, etching the copper plate, selectively applying a layer of solder resist, defining a cavity opening by punching, routing or etching, attaching a heat sink, forming dam rings and protecting the laminate by mold compound, attaching a die and bonding gold wires and encapsulating the cavity opening by encapsulate and attaching solder balls. In particular, a metal plate substitutes for a BT resin material to achieve low packaging cost and increasing the heat dissipating efficiency. A transfer flat type ball grid array method is employed to achieve an effect of fine circuitry and each single substrate is processed and tested individually.

Abstract: A BGA packaging method for an IC includes steps of providing a first dry film to a copper plate, plating nickel-copper to form circuits on one side of the copper plate, providing a second dry film, selectively plating nickel-gold, removing the dry films, providing an insulating layer, providing a back plate, attaching a chip, wire bonding, encapsulating the chip and wires with plastic, etching copper, providing solder resist and attaching solder balls. By this method, a packaged IC with excellent electrical characteristics and heat dissipation can be obtained through a simple procedure.

Abstract: Methods for packaging TAB-BGA integrated circuits are disclosed, which mainly include steps of providing a double-sided polyimide; forming first dry film layers; sequentially performing a multi-layer electroplating operation of electro-coppering, electronickelling, gold plating and electronickelling again (or electronickelling and gold plating, or electro-coppering and electronickelling); removing the first dry film layers; serving a lower second dry film layer as a mask for etching a bottom thin copper layer to define a plurality of predetermined openings; serving the bottom thin copper layer as a mask for applying a laser etching operation to the polyimide substrate to define holes without totally penetrating the polyimide substrate; applying an electrolytic plating operation to the holes for forming protruding contacts; etching the exposed top thin copper layer and/or removing a nickel-electroplated layer; and respectively defining a chip installation hole and a plurality of through holes by performing a l

Abstract: A solid tape automated bonding method includes steps of: applying a pattern of a first dry film on a first portion of a copper plate; forming wiring; forming bumps; removing dry film and exposing the wiring and the bumps; selectively laminating an insulator layer onto portions of the exposed copper plate and the wiring; laminating a metal layer on the insulator layer; applying glue on the metal layer, the bumps, and respective exposed portions of the wiring and the copper plate; etching the copper plate thus exposing one side of the wiring as ball pads and exposing one side of the insulator layer; coating solder resist on the exposed bottom side of the insulator layer; removing the glue; attaching a die against the bumps; applying mold compound onto the die so as to fix the die in place; and attaching solder balls onto the ball pads. This method provides relatively high density of wiring and simplification in manufacturing.