Abstract: A system and method for providing a sustained, peak performance computing architecture is provided. A hardware processing architecture is provided for performing repeated algorithm iterations, wherein each of the algorithm iterations is performed on a parallel set of algorithm input data. The architecture includes a memory arranged to store the algorithm input data in parallel, contiguous bit locations. A parallel execution module having a plurality of functional execution units is provided, each of the functional execution units being configured to perform a preassigned function dictated by the algorithm on predetermined bits of each iterative parallel set of algorithm input data.