Abstract: A system, method and chip for transforming data through a Rung-Kutta integration of a single point on a plane defined by X, Y, and Z values along X, Y and Z axes from a travel time data volume. The system includes at least one memory bank and at least one alternate memory bank and at least one single cycle Runge-Kutta travel time generator in communication with the memory banks. The single cycle Runge-Kutta travel time generator reads data from the at least one memory bank, and transforms the data by performing a Runge-Kutta integration on points of a plane defined by X, Y, and Z values along X, Y and Z axes in a travel time data volume and slowness data to generate another plane of values with the integration carried forward by a half step; and writes the data back to the at least one alternate memory bank.

Abstract: A system and method for providing a sustained, peak performance computing architecture is provided. A hardware processing architecture is provided for performing repeated algorithm iterations, wherein each of the algorithm iterations is performed on a parallel set of algorithm input data. The architecture includes a memory arranged to store the algorithm input data in parallel, contiguous bit locations. A parallel execution module having a plurality of functional execution units is provided, each of the functional execution units being configured to perform a preassigned function dictated by the algorithm on predetermined bits of each iterative parallel set of algorithm input data.