Abstract: An interface modem for use in a broadband local area data network with collision avoidance protocol. The data link controller features hardware acknowledge circuitry that acknowledges the receipt of a perfect data packet immediately upon receipt thereof without request to or assistance by the client data processing unit. The DLC prepares the acknowledgement packet from the incoming data packet and places it on the data link without going through a line acquisition protocol. Each received acknowledgment packet is placed in a transmit buffer at a known location relative to the data packet which was just transmitted, for which it is an acknowledgment so that each acknowledgment packet may be located in less time by the client data processing unit. The acknowledgment packets are logically part of the transmit process and are therefore placed in the transmit buffer.

Abstract: A modem for a single frequency, modulated RF carrier local data network for a distributed data processing system and a method for line acquisition and contention resolution. The protocol established for line acquisition and contention resolution is implemented by a modem controller. The controller causes the receiver section to listen for foreign carriers to determine when the line is busy. When the client device of the modem desires to send a data packet to another unit, the modem controller causes the receiver to listen for a certain pre-burst period and then causes the transmitter to send a burst of RF carrier out on the line and simultaneously causes the receiver to listen to the line for interference beating, i.e. changes in amplitude on the line which indicates another unit is requesting the line. To insure beat patterns, the frequency of the burst carrier is swept over a range during the burst. If a contention is found, a resolution thereof is made utilizing a random delay and retry protocol.

Abstract: An apparatus is disclosed for error correcting during the refresh cycle of a dynamic memory. The apparatus includes a refresh counter means for supplying row addresses to a dynamic memory during refresh cycles and decoder circuitry for supplying row address and column address strobe signals to the memory to cause it to refresh rows sequentially and pick one word out of each refreshed row for error correcting.Also disclosed is a computer system utilizing a semiconductor memory with on-board error correcting circuitry using hamming codes to generate check bits from which they are generated. Upon access of data from the memory, the check bits are used to locate and correct single bit errors and detect some double bit errors. A CPU is disclosed which incorporates a spot check system stored in non-volatile memory to independently randomly generate syndrome bits from data accessed from memory and compare these syndrome bits to the check bits stored with the accessed data.

Abstract: An improved distributed input/output system is disclosed for controlling numerous high speed peripheral devices (both low speed, medium speed, and high speed) and the transfer of data signals, status signals, and control signals between those devices and a general purpose digital computer. The control system described includes a direct-memory-access multiplexer which can accommodate a plurality of low or medium-speed input/output services and also high-speed input/output devices under the control of separate programmable microcoded peripheral-unit controllers. The direct-memory-access multiplexer of this invention is fully compatible with controllers that can also be used with an indirect-memory access multiplexer. Each controller, being an element of a distributed system, is adapted to be located at an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable.

Abstract: A special broadcast communication link is provided between a central processing unit and plural computer peripheral devices, the communication link being in addition to normal data and addressing communication lines, and providing a distributed control channel which is used to inhibit selected classes of interrupt signals from controllers associated with the peripheral devices in accordance with an interrupt classification system. This communication channel permits the central processing unit to issue a data command which selectively inhibits the peripheral devices from issuing selected classes of interrupt signals.

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series.

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series.

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to cary both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series.

Abstract: A modular minicomputer is provided which is assembled from a central processor unit module and a plurality of memory modules. Small calculators on the memory modules are so interlocked that when the computer is powered up, memory address boundaries are calculated automatically. As a result, the bank of memory modules appears to the central processing unit the same as a single large memory unit.

Abstract: A modular minicomputer is provided which is assembled from a central processor unit module and a plurality of memory modules. Small calculators on the memory modules are so interlocked that when the computer is powered up, memory address boundaries are calculated automatically. As a result, the bank of memory modules appears to the central processing unit the same as a single large memory unit.