Abstract: A novel and useful apparatus for and method of communicating time related messages between multiple devices wherein each device operates using a different time base. The invention can be applied to multi-mode cellular handsets that implement multiple radio access technologies (RATs). Messages communicated between the RATs are time synchronized using a common time base that is shared among all the RATs in the system. The creation of the shared time base is based on an interrupt signal referred to as a “sync event”. The interrupt signal is generated by at least one of the devices and received by all the other devices. The local time is stored in a snapshot register and is used by each respective device as the basis to perform conversions between local and common time, common time being the time base that is shared by all the devices in the system. This ‘synchronizes’ the devices since they all took a snapshot of their respective local timers at substantially the same time.

Abstract: A novel and useful apparatus for and method of single antenna interference cancellation (SAIC) in a wireless communications system. A class of algorithms is disclosed for Downlink Advanced Receiver Performance (DARP) receivers based on a novel metric calculation used during equalization and optionally in other portions of the receiver as well, e.g., soft value generation. A DARP receiver for 8PSK EDGE modulation is presented wherein the interfering signals comprise GMSK modulated signals. The modified metric takes into account the rotation remaining in the noise component of the received signal after de-rotation of the 8PSK signal. Considering the interferer to be a GMSK signal, the I/Q elements of the noise are correlated and this fact is used to modify the decision rule for the received signal thus improving the performance of the equalizer. The model is further extended to take into account temporal error correlation.

Abstract: A real-time optimizing information transfer and interrupt event scheduling scheme for a communications transceiver incorporating multiple processing elements. The scheme is particularly applicable for use in UMTS based communications transceivers, i.e. W-CDMA transceivers adapted for User Equipment (UE). The interrupt scheduling scheme of the present invention is operative to perform the scheduling of interrupts used to configure a data transfer device to effect the timely transfer of data from a hardware based chip rate processor to a memory buffer for subsequent processing by software running on a DSP or other processor platform.

Abstract: A novel and useful apparatus for and method of determining the channel order and channel estimate in a communications system. The present invention is suitable for use with a wide range of channels and is particularly useful in estimating wireless channels such as GSM and other types of cellular channels. A channel estimate is performed on the entire received training sequence. Those taps having an energy larger than the energy of a channel estimation error quantity are selected for the final channel estimation model. The estimation error is calculated by dividing the complete received training sequence into two different portions, wherein both portions are of equal size. A channel estimate is used to calculate the channel estimate of both portions which are then used to calculate the channel estimation error quantity.

Abstract: A method and apparatus for estimating channel tap delays of multipath components in a CDMA received signal. The search for the tap delays are split into two phases namely, a phase 1 and a phase 2 search. The phase 1 search is a coarse resolution quick search adapted to generate a rough estimate of the location of the tap delays. During this phase, the candidate codes are summed and the input signal correlated with the code sum creating an ambiguity in the code associated with the multipath. A finer resolution slower phase 2 search resolves the code ambiguity present in the initial rough estimates of the phase 1 search. Additional phase 2 correlations may be performed to implement a code-tracking loop.

Abstract: A novel and useful channel tracking mechanism operative to generate channel estimate updates on blocks of samples during reception of a message. The tracking mechanism is based on the weighted recursive least squares algorithm and implements the estimation process by recursively updating channel model parameters upon the arrival of new sample data. The mechanism is operative to update channel estimate information once per sample block. An interblock exponential weighting factor is also applied. The block length is chosen short enough to enable good tracking performance while being sufficiently long enough to minimize the overhead of generating preliminary decisions and of updating precalculated tables in the equalizer. The method of the invention can be performed in either hardware or software. A computer comprising a processor, memory, etc. is operative to execute software adapted to perform the channel tracking method of the present invention.

Abstract: A reduced complexity correlator that enables the re-use of the most complex portions of a correlator, namely the multiplier and adder. The correlator of the present invention is especially well-suited for use in CDMA and W-CDMA spread spectrum communication systems that require the use of numerous correlators in their operation. Multiple input samples, multiple codes and integration results are stored in shift registers and circularly shifted and clocked out at appropriate clock rates such that the multiplication and accumulation steps of the correlation process are synchronized.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N?1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N-1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: An apparatus for and method of generating normalized soft decision information output from an inner decoder (i.e. equalizer) in a communications receiver. The invention is operative to normalize the soft decision information before it enters a soft outer decoder. The normalization is performed using a noise power estimate that is dynamically calculated in response to changing noise statistics on the channel. The normalized soft decision output is then applied to the soft outer decoder thus realizing maximum performance therefrom. The noise power estimate is derived from the training sequence and/or the data portion of the received signal. Both types of estimates are calculated. A binary or smoothly weighted average is calculated using both types of estimates. The weighting factor is determined based on one or more performance metrics, such as the Signal to Noise Ratio (SNR).

Abstract: A novel and useful apparatus for and method of I/Q gain mismatch compensation for use in a communications receiver. The invention is operative to calculate an estimate of the I/Q gain mismatch. Each input sample is subsequently multiplied by the inverse of the estimate to generate compensated samples. The training sequence portion of the uncompensated input samples is used to generate the I/Q gain mismatch estimate. In accordance with the present invention, the H matrix used in calculating the gain mismatch estimate is pre-calculated for several channel lengths and stored in memory. An estimate of the channel is generated which provides the channel length and the location in the input sample buffer of the first training sequence sample to be used in calculating the gain mismatch estimate. The channel length is used to determine the number of training sequence samples to be used and to select one of the previously calculated H matrices.

Abstract: An apparatus for and method of converting soft symbol decision information into soft bit decision information that overcomes the disadvantages of the prior art. The invention is adapted to receive M soft symbol values where each symbol represents m bits (M=2m). The output for each symbol comprises m soft values of bits representing the symbol. The invention is operative to convert the soft symbol values to soft bit values using the log likelihood ratios (LLRs) of a bit and a symbol expressed as conditional probabilities. The method of the invention is presented which can be performed in either hardware or software. A computer comprising a processor, memory, etc. is operative to execute software adapted to perform the soft symbol to bit conversion method of the present invention.

Abstract: A novel and useful apparatus for and method of determining the channel order and channel estimate in a communications system such as a wireless communication system including cellular and cordless. Such channels are typically characterized by rapidly changing impulse response and their taps can be modeled as zero-mean, complex, Gaussian random processes. A sufficiently long, initial channel estimate of length is performed so as to ensure that the actual channel taps will be contained in the estimated taps thus making certain that the equalizer will effectively eliminate intersymbol interference. Channel estimation is performed during each burst using the training sequence transmitted in the middle of the burst. The tap energies are averaged so as to track slow variations in the pattern of resultant channel taps. A noise floor is calculated using the lowest averaged taps and a threshold is computed based thereon and applied to the average taps.

Abstract: A novel and useful apparatus for and method of DC offset compensation for use in a communications receiver. The invention is operative to calculate an estimate of the DC offset which is subsequently subtracted from each input sample to generate compensated samples. The training sequence portion of the uncompensated input samples is used to generate an estimate of the DC offset. The vector used in calculating the offset estimate is pre-calculated for several channel lengths and stored in memory. An estimate of the channel is generated which provides the channel length and the location in the input sample buffer of the first training sequence sample to be used in calculating the offset estimate. The channel length is used to determine the number of training sequence samples to be used and to select one of the previously calculated vectors.

Abstract: The system utilizes host signal processing techniques applicable to cellular communication system devices which are integrated with a system incorporating a general purpose CPU running a multitasking operating system. A RF receiver processes the signals to generate a receive signal, the RF module performs RF transmit processing on a transmit signal and generates the transmit wireless signal from it. A host processor communicates data, status and control information with the RF device via a bus, the host processor includes host based software application and a host based modem application. The receive signal generated by the RF module over the bus and generates receive data in response to it input to the software application at a output by the software application is received and generates the transmit signal in response to it, sending the transmit signal to the RF module over the bus. The figure shows a block diagram illustrating an analog cellular communications systems tuned for data communication.

Abstract: A novel and useful whitening matched filter (WMF) for use in a communications receiver. The WMF is constructed by cascading a matched filter and a noise-whitening filter. The response of the matched filter is derived from the time reversed complex conjugate of the channel impulse response. The whitening filter is derived by extracting the minimum phase portion of the mixed phase channel impulse response using homomorphic deconvolution. The whitening filter is implemented using either an FIR or IIR filter adapted to process the data received before and after the training sequence using a minimum phase system in a direction in time opposite to that of the direction of corresponding data sample processing performed by the equalizer.

Abstract: A novel data transfer scheme for efficiently transferring data between multiple data generating processing units in a processing element wherein each processing unit may generate data at different rates. The data output of each processing unit is multiplexed into a single data stream and written to a memory buffer. A centralized software processor such as a CPU or DSP implements a demultiplexer operative to read the contents of the input buffer, demultiplex the data and distribute it to individual unit buffers thus recreating the original data streams generating by each of the processing units. The multiplexed data stream is generated by partitioning the outputs of the data generating processing units into multiple multiplexer groups based on individual data rates. The outputs of the various groups are collected by a multiplexer and used to build a single data stream having a well-defined structure.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity that and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N−1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: An apparatus for and method of generating soft decision information from a sequence of hard symbol decisions output from a decoder in a concatenated communications receiver. Soft symbol decisions are computed given hard symbol decisions from the equalizer, channel estimation information (i.e. FIR filter taps used to estimate the channel), and the input samples received from the channel. The log likelihood ratio (LLR) for all symbol possibilities is calculated by computing the conditional probability of the input sample sequence given the hard symbol decision sequence. The noise variance is optionally used in computing the soft output values, thus improving the overall performance of the receiver. In one embodiment, symbol vectors are calculated beforehand and stored in a table. An error vector calculator functions to calculate an error vector that is applied to soft output calculation units. Each soft output calculation unit functions to generate a soft output value for a particular symbol candidate.

Abstract: A novel data transfer scheme for efficiently transferring data between multiple data generating processing units in a processing element wherein each processing unit may generate data at different rates. The data output of each processing unit is multiplexed into a single data stream and written to a memory buffer. A centralized software processor such as a CPU or DSP implements a demultiplexer operative to read the contents of the input buffer, demultiplex the data and distribute it to individual unit buffers thus recreating the original data streams generating by each of the processing units. The multiplexed data stream is generated by partitioning the outputs of the data generating processing units into multiple multiplexer groups based on individual data rates. The outputs of the various groups are collected by a multiplexer and used to build a single data stream having a well-defined structure.