Abstract: A method and apparatus for selectively accelerating network communications provides improved operation of network communications through channels with long delays, such as a satellite communications channel. A configuration management mechanism provides a selection of acceleration configuration for particular addresses of devices that may communicate through the communications channels. Acceleration may be bypassed for particular addresses or classes of devices within the network and priorities may be assigned, permitting a cut-off of acceleration when a threshold number of sessions is reached. The method and system may also allow a higher priority class of session to preempt lower priority session by removing resources from the lower priority session and assigning them to the higher priority session. The data rate of the lower priority session is then lowered (due to the absence of acceleration or reduced buffer size) to reduce traffic flow.

Abstract: A digital summing phase-lock loop circuit with sideband control provides high accuracy and high speed acquisition in a multi-loop frequency synthesizer. A digital phase comparator is used to control a voltage-controlled oscillator in response to inputs from multiple external loops. An initial sweep condition is set by a sweep control circuit to provide resolution of lock ambiguities in the multiple external loops. Sideband selection may be performed by selecting on of an inverted or non-inverted output of the digital phase comparator.