Patents Assigned to Concurrent Computer Corporation
  • Patent number: 4694194
    Abstract: A pulsed power supply having a filter output and a battery backup includes electronic apparatus to sense when the AC source is failing. When the pulsed supply output has the same pulses as that which would be produced by the battery, the supply switches to battery backup mode. As the AC source returns, the supply switches to AC supply mode when the AC is at a level where the pulses produced by the supply would be the same as are actually being produced by the battery backup.
    Type: Grant
    Filed: November 4, 1985
    Date of Patent: September 15, 1987
    Assignee: Concurrent Computer Corporation
    Inventors: Allen Hansel, Ermand Centofanti, Thiagarajan Natarajan
  • Patent number: 4653019
    Abstract: A multi-function high speed barrel shifter comprising three functional levels. The first level performs 1/4 word shifts by a selectable amount. The second level performs 1/8 word shifts on the portion of the word to be shifted and, where desired, fills the remainder of its output with fill bits. The third level performs 1/32 of a data word shift. All shifting and filling are controlled by an input control signal which specifies the operation, direction and shift amount. The circuit is easily complimented in LSI Technology and is easily cascaded to double the size of the data word handled thereby.
    Type: Grant
    Filed: April 19, 1984
    Date of Patent: March 24, 1987
    Assignee: Concurrent Computer Corporation
    Inventors: James E. Hodge, Kenneth C. Yeager
  • Patent number: 4636944
    Abstract: A multi-level priority micro-interrupt controller for a micro-program controlled computer handles a plurality of interrupt signals at a plurality of levels of priority, wherein only one interrupt signal for each level of priority may be active at any moment. When an interrupt occurs which has a higher priority than that of the interrupt currently being handled, the control store address of the next instruction to be executed is stacked and the interrupt handler subroutine for the higher priority interrupt is initiated. When an interrupt occurs which has a lower priority than that of the interrupt currently being handled, it is queued. After an interrupt has been handled, the stack is popped and execution is resumed at the control store address at the top of the stack. The control store address of the interrupt handler subroutine for a particular interrupt is decoded from the interrupt signals in two parts, the second part also being used to control the branching to the interrupt handler subroutine.
    Type: Grant
    Filed: January 17, 1984
    Date of Patent: January 13, 1987
    Assignee: Concurrent Computer Corporation
    Inventor: James E. Hodge